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Renaming xe::cpu::frontend to xe::cpu::ppc.

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This commit is contained in:
Ben Vanik
2015-12-14 21:17:55 -08:00
parent 9273359cdd
commit 15816327b4
225 changed files with 196 additions and 204 deletions
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153
src/xenia/cpu/ppc/testing/instr_srad.s Normal file
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test_srad_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_srad_1_constant:
li r4, 1
li r5, 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_srad_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_srad_2_constant:
li r4, -1
li r5, 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_srad_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_srad_3_constant:
li r4, -1
li r5, 1
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_srad_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 62
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 62
#_ REGISTER_OUT r6 1
test_srad_4_constant:
li r4, -1
li r5, 62
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 62
#_ REGISTER_OUT r6 1
test_srad_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 63
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
#_ REGISTER_OUT r6 1
test_srad_5_constant:
li r4, -1
li r5, 63
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
#_ REGISTER_OUT r6 1
test_srad_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 64
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
#_ REGISTER_OUT r6 1
test_srad_6_constant:
li r4, -1
li r5, 64
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
#_ REGISTER_OUT r6 1
test_srad_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 100
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
#_ REGISTER_OUT r6 1
test_srad_7_constant:
li r4, -1
li r5, 100
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
#_ REGISTER_OUT r6 1