From 15f61a1a109e80158f3fb39aa041abd52d60fd27 Mon Sep 17 00:00:00 2001 From: "Herman S." <429230+has207@users.noreply.github.com> Date: Tue, 14 Oct 2025 14:49:56 +0900 Subject: [PATCH] [x64] Fix vector mask issue and add missing tests --- src/xenia/cpu/backend/x64/x64_seq_vector.cc | 10 +++- src/xenia/cpu/ppc/testing/instr_vsrab.s | 55 ++++++++++++++++++ src/xenia/cpu/ppc/testing/instr_vsrah.s | 64 +++++++++++++++++++++ src/xenia/cpu/ppc/testing/instr_vsraw.s | 63 ++++++++++++++++++++ src/xenia/cpu/ppc/testing/instr_vsrb.s | 47 +++++++++++++++ src/xenia/cpu/ppc/testing/instr_vsrh.s | 48 ++++++++++++++++ src/xenia/cpu/ppc/testing/instr_vsrw.s | 55 ++++++++++++++++++ 7 files changed, 340 insertions(+), 2 deletions(-) create mode 100644 src/xenia/cpu/ppc/testing/instr_vsrab.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vsraw.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vsrb.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vsrw.s diff --git a/src/xenia/cpu/backend/x64/x64_seq_vector.cc b/src/xenia/cpu/backend/x64/x64_seq_vector.cc index fbdcd43e9..cc2f2cb46 100644 --- a/src/xenia/cpu/backend/x64/x64_seq_vector.cc +++ b/src/xenia/cpu/backend/x64/x64_seq_vector.cc @@ -1111,6 +1111,7 @@ struct VECTOR_SHL_V128 e.L(looper); e.movzx(e.ecx, e.word[e.rsp + stack_offset_src2 + e.rdx]); + e.and_(e.cl, 0xF); // Mask shift count to 4 bits (0-15) for word shifts e.shl(e.word[e.rsp + stack_offset_src1 + e.rdx], e.cl); @@ -1205,6 +1206,7 @@ struct VECTOR_SHL_V128 e.L(looper); e.mov(e.ecx, e.dword[e.rsp + stack_offset_src2 + e.rdx]); + e.and_(e.cl, 0x1F); // Mask shift count to 5 bits (0-31) for dword shifts e.shl(e.dword[e.rsp + stack_offset_src1 + e.rdx], e.cl); @@ -1313,6 +1315,7 @@ struct VECTOR_SHR_V128 // movzx is to eliminate any possible dep on previous value of rcx at start // of loop e.movzx(e.ecx, e.byte[e.rsp + stack_offset_src2 + e.rdx]); + e.and_(e.cl, 7); // Mask shift count to 3 bits (0-7) for byte shifts // maybe using a memory operand as the left side isn't the best idea lol, // still better than callnativesafe though agners docs have no timing info // on shx [m], cl so shrug @@ -1392,7 +1395,7 @@ struct VECTOR_SHR_V128 e.L(looper); e.movzx(e.ecx, e.word[e.rsp + stack_offset_src2 + e.rdx]); - + e.and_(e.cl, 0xF); // Mask shift count to 4 bits (0-15) for word shifts e.shr(e.word[e.rsp + stack_offset_src1 + e.rdx], e.cl); e.add(e.edx, 2); @@ -1492,6 +1495,7 @@ struct VECTOR_SHR_V128 e.L(looper); e.mov(e.ecx, e.dword[e.rsp + stack_offset_src2 + e.rdx]); + e.and_(e.cl, 0x1F); // Mask shift count to 5 bits (0-31) for dword shifts e.shr(e.dword[e.rsp + stack_offset_src1 + e.rdx], e.cl); e.add(e.edx, 4); @@ -1612,6 +1616,7 @@ struct VECTOR_SHA_V128 // movzx is to eliminate any possible dep on previous value of rcx at start // of loop e.movzx(e.ecx, e.byte[e.rsp + stack_offset_src2 + e.rdx]); + e.and_(e.cl, 7); // Mask shift count to 3 bits (0-7) for byte shifts // maybe using a memory operand as the left side isn't the best idea lol, // still better than callnativesafe though agners docs have no timing info // on shx [m], cl so shrug @@ -1691,7 +1696,7 @@ struct VECTOR_SHA_V128 e.L(looper); e.movzx(e.ecx, e.word[e.rsp + stack_offset_src2 + e.rdx]); - + e.and_(e.cl, 0xF); // Mask shift count to 4 bits (0-15) for word shifts e.sar(e.word[e.rsp + stack_offset_src1 + e.rdx], e.cl); e.add(e.edx, 2); @@ -1775,6 +1780,7 @@ struct VECTOR_SHA_V128 e.L(looper); e.mov(e.ecx, e.dword[e.rsp + stack_offset_src2 + e.rdx]); + e.and_(e.cl, 0x1F); // Mask shift count to 5 bits (0-31) for dword shifts e.sar(e.dword[e.rsp + stack_offset_src1 + e.rdx], e.cl); e.add(e.edx, 4); diff --git a/src/xenia/cpu/ppc/testing/instr_vsrab.s b/src/xenia/cpu/ppc/testing/instr_vsrab.s new file mode 100644 index 000000000..cfff20d32 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vsrab.s @@ -0,0 +1,55 @@ +test_vsrab_1: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vsrab v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + +test_vsrab_2: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101] + vsrab v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101] + +test_vsrab_3: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707] + vsrab v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707] + +test_vsrab_4: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808] + vsrab v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808] + +test_vsrab_5: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909] + vsrab v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909] + +test_vsrab_6: + #_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F] + #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101] + vsrab v3, v3, v4 + blr + #_ REGISTER_OUT v3 [3F3F3F3F, 3F3F3F3F, 3F3F3F3F, 3F3F3F3F] + #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101] + +test_vsrab_7: + #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080] + #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101] + vsrab v3, v3, v4 + blr + #_ REGISTER_OUT v3 [C0C0C0C0, C0C0C0C0, C0C0C0C0, C0C0C0C0] + #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101] diff --git a/src/xenia/cpu/ppc/testing/instr_vsrah.s b/src/xenia/cpu/ppc/testing/instr_vsrah.s index beb42906f..1f7f64813 100644 --- a/src/xenia/cpu/ppc/testing/instr_vsrah.s +++ b/src/xenia/cpu/ppc/testing/instr_vsrah.s @@ -1,4 +1,68 @@ test_vsrah_1: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vsrah v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + +test_vsrah_2: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001] + vsrah v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001] + +test_vsrah_3: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F] + vsrah v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F] + +test_vsrah_4: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010] + vsrah v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010] + +test_vsrah_5: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00090009, 00090009, 00090009, 00090009] + vsrah v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00090009, 00090009, 00090009, 00090009] + +test_vsrah_6: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011] + vsrah v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011] + +test_vsrah_7: + #_ REGISTER_IN v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF] + #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001] + vsrah v3, v3, v4 + blr + #_ REGISTER_OUT v3 [3FFF3FFF, 3FFF3FFF, 3FFF3FFF, 3FFF3FFF] + #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001] + +test_vsrah_8: + #_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000] + #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001] + vsrah v3, v3, v4 + blr + #_ REGISTER_OUT v3 [C000C000, C000C000, C000C000, C000C000] + #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001] + +test_vsrah_9: #_ REGISTER_IN v3 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v4 [000D000D, 000D000D, 000D000D, 000D000D] vsrah v5, v3, v4 diff --git a/src/xenia/cpu/ppc/testing/instr_vsraw.s b/src/xenia/cpu/ppc/testing/instr_vsraw.s new file mode 100644 index 000000000..68b885c7e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vsraw.s @@ -0,0 +1,63 @@ +test_vsraw_1: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vsraw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + +test_vsraw_2: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] + vsraw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001] + +test_vsraw_3: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F] + vsraw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F] + +test_vsraw_4: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020] + vsraw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020] + +test_vsraw_5: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000009, 00000009, 00000009, 00000009] + vsraw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000009, 00000009, 00000009, 00000009] + +test_vsraw_6: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021] + vsraw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021] + +test_vsraw_7: + #_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] + #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] + vsraw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [3FFFFFFF, 3FFFFFFF, 3FFFFFFF, 3FFFFFFF] + #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001] + +test_vsraw_8: + #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000] + #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] + vsraw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000] + #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001] diff --git a/src/xenia/cpu/ppc/testing/instr_vsrb.s b/src/xenia/cpu/ppc/testing/instr_vsrb.s new file mode 100644 index 000000000..168dcd294 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vsrb.s @@ -0,0 +1,47 @@ +test_vsrb_1: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vsrb v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + +test_vsrb_2: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101] + vsrb v3, v3, v4 + blr + #_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F] + #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101] + +test_vsrb_3: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707] + vsrb v3, v3, v4 + blr + #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101] + #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707] + +test_vsrb_4: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808] + vsrb v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808] + +test_vsrb_5: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909] + vsrb v3, v3, v4 + blr + #_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F] + #_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909] + +test_vsrb_6: + #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080] + #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101] + vsrb v3, v3, v4 + blr + #_ REGISTER_OUT v3 [40404040, 40404040, 40404040, 40404040] + #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101] diff --git a/src/xenia/cpu/ppc/testing/instr_vsrh.s b/src/xenia/cpu/ppc/testing/instr_vsrh.s index 33210f8ce..3bb8ceed9 100644 --- a/src/xenia/cpu/ppc/testing/instr_vsrh.s +++ b/src/xenia/cpu/ppc/testing/instr_vsrh.s @@ -1,4 +1,52 @@ test_vsrh_1: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vsrh v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + +test_vsrh_2: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001] + vsrh v3, v3, v4 + blr + #_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF] + #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001] + +test_vsrh_3: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F] + vsrh v3, v3, v4 + blr + #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001] + #_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F] + +test_vsrh_4: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010] + vsrh v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010] + +test_vsrh_5: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00090009, 00090009, 00090009, 00090009] + vsrh v3, v3, v4 + blr + #_ REGISTER_OUT v3 [007F007F, 007F007F, 007F007F, 007F007F] + #_ REGISTER_OUT v4 [00090009, 00090009, 00090009, 00090009] + +test_vsrh_6: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011] + vsrh v3, v3, v4 + blr + #_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF] + #_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011] + +test_vsrh_7: #_ REGISTER_IN v3 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v4 [000D000D, 000D000D, 000D000D, 000D000D] vsrh v5, v3, v4 diff --git a/src/xenia/cpu/ppc/testing/instr_vsrw.s b/src/xenia/cpu/ppc/testing/instr_vsrw.s new file mode 100644 index 000000000..bfe2a79d4 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vsrw.s @@ -0,0 +1,55 @@ +test_vsrw_1: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vsrw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + +test_vsrw_2: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] + vsrw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] + #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001] + +test_vsrw_3: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F] + vsrw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] + #_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F] + +test_vsrw_4: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020] + vsrw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020] + +test_vsrw_5: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000009, 00000009, 00000009, 00000009] + vsrw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [007FFFFF, 007FFFFF, 007FFFFF, 007FFFFF] + #_ REGISTER_OUT v4 [00000009, 00000009, 00000009, 00000009] + +test_vsrw_6: + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021] + vsrw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] + #_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021] + +test_vsrw_7: + #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000] + #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] + vsrw v3, v3, v4 + blr + #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]