[GPU] Eliminate unused shader I/O, UCP culling, centroid on Vulkan
For more optimal usage of exports and the parameter cache on the host regardless of how effective the optimizations in the host GPU driver are. Also reserve space for Vulkan/Metal/D3D11-specific HostVertexShaderTypes to use one more bit for the host vertex shader type in the shader modification bits, so that won't have to be done in the future as that would require invalidating shader storages (which are invalidated by this commit) again.
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@@ -34,7 +34,7 @@ class SpirvShaderTranslator : public ShaderTranslator {
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// TODO(Triang3l): Change to 0xYYYYMMDD once it's out of the rapid
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// prototyping stage (easier to do small granular updates with an
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// incremental counter).
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static constexpr uint32_t kVersion = 4;
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static constexpr uint32_t kVersion = 5;
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enum class DepthStencilMode : uint32_t {
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kNoModifiers,
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@@ -46,6 +46,10 @@ class SpirvShaderTranslator : public ShaderTranslator {
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};
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struct {
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// uint32_t 0.
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// Interpolators written by the vertex shader and needed by the pixel
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// shader.
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uint32_t interpolator_mask : xenos::kMaxInterpolators;
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// Dynamically indexable register count from SQ_PROGRAM_CNTL.
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uint32_t dynamic_addressable_register_count : 8;
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// Pipeline stage and input configuration.
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@@ -53,6 +57,12 @@ class SpirvShaderTranslator : public ShaderTranslator {
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: Shader::kHostVertexShaderTypeBitCount;
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} vertex;
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struct PixelShaderModification {
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// uint32_t 0.
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// Interpolators written by the vertex shader and needed by the pixel
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// shader.
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uint32_t interpolator_mask : xenos::kMaxInterpolators;
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uint32_t interpolators_centroid : xenos::kMaxInterpolators;
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// uint32_t 1.
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// Dynamically indexable register count from SQ_PROGRAM_CNTL.
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uint32_t dynamic_addressable_register_count : 8;
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uint32_t param_gen_enable : 1;
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@@ -66,7 +76,10 @@ class SpirvShaderTranslator : public ShaderTranslator {
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} pixel;
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uint64_t value = 0;
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Modification(uint64_t modification_value = 0) : value(modification_value) {}
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explicit Modification(uint64_t modification_value = 0)
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: value(modification_value) {
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static_assert_size(*this, sizeof(value));
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}
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};
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enum : uint32_t {
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@@ -346,6 +359,12 @@ class SpirvShaderTranslator : public ShaderTranslator {
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current_shader().implicit_early_z_write_allowed();
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}
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uint32_t GetModificationInterpolatorMask() const {
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Modification modification = GetSpirvShaderModification();
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return is_vertex_shader() ? modification.vertex.interpolator_mask
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: modification.pixel.interpolator_mask;
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}
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// Returns UINT32_MAX if PsParamGen doesn't need to be written.
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uint32_t GetPsParamGenInterpolator() const;
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@@ -529,8 +548,6 @@ class SpirvShaderTranslator : public ShaderTranslator {
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spv::Id type_float_vectors_[4];
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};
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spv::Id type_interpolators_;
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spv::Id const_int_0_;
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spv::Id const_int4_0_;
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spv::Id const_uint_0_;
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@@ -591,12 +608,16 @@ class SpirvShaderTranslator : public ShaderTranslator {
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// PS, only when needed - bool.
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spv::Id input_front_facing_;
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// VS output or PS input, only when needed - type_interpolators_.
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// The Qualcomm Adreno driver has strict requirements for stage linkage - if
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// this is an array in one stage, it must be an array in the other (in case of
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// Xenia, including geometry shaders); it must not be an array in one and just
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// elements in consecutive locations in another.
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spv::Id input_output_interpolators_;
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// VS output or PS input, only the ones that are needed (spv::NoResult for the
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// unneeded interpolators), indexed by the guest interpolator index - float4.
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// The Qualcomm Adreno driver has strict requirements for stage linkage - as
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// Xenia uses separate variables, not an array (so the interpolation
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// qualifiers can be applied to each element separately), the interpolators
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// must also be separate variables in the other stage, including the geometry
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// shader (not just an array assuming that consecutive locations will be
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// linked as consecutive array elements, on Qualcomm, they won't be linked at
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// all).
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std::array<spv::Id, xenos::kMaxInterpolators> input_output_interpolators_;
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enum OutputPerVertexMember : unsigned int {
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kOutputPerVertexMemberPosition,
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