From 1b2557498699ec7a9165ad2928335123f8409db1 Mon Sep 17 00:00:00 2001 From: "Herman S." <429230+has207@users.noreply.github.com> Date: Sun, 19 Oct 2025 13:42:59 +0900 Subject: [PATCH] [Testing] Add a lot more missing instruction tests --- src/xenia/cpu/ppc/testing/instr_addx.s | 90 +++++++++++++++++++ src/xenia/cpu/ppc/testing/instr_cntlzdx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_cntlzwx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_dcbf.s | 31 +++++++ src/xenia/cpu/ppc/testing/instr_dcbst.s | 31 +++++++ src/xenia/cpu/ppc/testing/instr_dcbt.s | 31 +++++++ src/xenia/cpu/ppc/testing/instr_dcbtst.s | 31 +++++++ src/xenia/cpu/ppc/testing/instr_dcbz.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_dcbz128.s | 28 ++++++ src/xenia/cpu/ppc/testing/instr_divdx.s | 89 ++++++++++++++++++ src/xenia/cpu/ppc/testing/instr_eieio.s | 13 +++ src/xenia/cpu/ppc/testing/instr_eqvx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_extsbx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_extshx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_extswx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fabsx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_faddsx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_faddx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_fcfidx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fcmpo.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_fcmpu.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_fctidx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fctidzx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fctiwx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fctiwzx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fdivsx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_fdivx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_fmaddsx.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_fmaddx.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_fmrx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fmsubsx.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_fmsubx.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_fmulsx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_fmulx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_fnabsx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fnegx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fnmaddsx.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_fnmaddx.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_fnmsubsx.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_fnmsubx.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_fresx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_frspx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_frsqrtex.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fselx.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_fsqrtsx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fsqrtx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_fsubsx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_fsubx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_icbi.s | 31 +++++++ src/xenia/cpu/ppc/testing/instr_isync.s | 13 +++ src/xenia/cpu/ppc/testing/instr_lbz.s | 50 +++++++++++ src/xenia/cpu/ppc/testing/instr_lbzu.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_ld.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_ldu.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_lfd.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_lfs.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_lha.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_lhau.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_lhbrx.s | 29 ++++++ src/xenia/cpu/ppc/testing/instr_lhz.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_lhzu.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_lmw.s | 23 +++++ src/xenia/cpu/ppc/testing/instr_lvlx128.s | 18 ++++ src/xenia/cpu/ppc/testing/instr_lvlxl128.s | 9 ++ src/xenia/cpu/ppc/testing/instr_lvrx128.s | 18 ++++ src/xenia/cpu/ppc/testing/instr_lvrxl128.s | 9 ++ src/xenia/cpu/ppc/testing/instr_lvsl128.s | 20 +++++ src/xenia/cpu/ppc/testing/instr_lvsr128.s | 20 +++++ src/xenia/cpu/ppc/testing/instr_lvxl128.s | 22 +++++ src/xenia/cpu/ppc/testing/instr_lwa.s | 45 ++++++++++ src/xenia/cpu/ppc/testing/instr_lwbrx.s | 29 ++++++ src/xenia/cpu/ppc/testing/instr_lwz.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_lwzu.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_lxarx.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_lxbrx.s | 59 ++++++++++++ src/xenia/cpu/ppc/testing/instr_mcrfs.s | 19 ++++ src/xenia/cpu/ppc/testing/instr_mcrxr.s | 19 ++++ src/xenia/cpu/ppc/testing/instr_mffsx.s | 31 +++++++ src/xenia/cpu/ppc/testing/instr_mfmsr.s | 11 +++ src/xenia/cpu/ppc/testing/instr_mfspr.s | 28 ++++++ src/xenia/cpu/ppc/testing/instr_mftb.s | 26 ++++++ src/xenia/cpu/ppc/testing/instr_mfvscr.s | 11 +++ src/xenia/cpu/ppc/testing/instr_mtcrf.s | 23 +++++ src/xenia/cpu/ppc/testing/instr_mtfsfix.s | 15 ++++ src/xenia/cpu/ppc/testing/instr_mtfsfx.s | 23 +++++ src/xenia/cpu/ppc/testing/instr_mtmsr.s | 11 +++ src/xenia/cpu/ppc/testing/instr_mtmsrd.s | 11 +++ src/xenia/cpu/ppc/testing/instr_mtspr.s | 25 ++++++ src/xenia/cpu/ppc/testing/instr_mulhdux.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_mulhdx.s | 82 +++++++++++++++++ src/xenia/cpu/ppc/testing/instr_mulhwux.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_mulhwx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_mulldx.s | 53 +++++++++++ src/xenia/cpu/ppc/testing/instr_negx.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_orcx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_rldclx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_rldcrx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_rldiclx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_rldicrx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_rldicx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_rldimix.s | 31 +++++++ src/xenia/cpu/ppc/testing/instr_rlwimix.s | 31 +++++++ src/xenia/cpu/ppc/testing/instr_rlwinmx.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_rlwnmx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_sldx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_slwx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_sradix.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_sradx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_srawix.s | 27 ++++++ src/xenia/cpu/ppc/testing/instr_srawx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_srdx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_srwx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_stb.s | 53 +++++++++++ src/xenia/cpu/ppc/testing/instr_std.s | 53 +++++++++++ src/xenia/cpu/ppc/testing/instr_stfd.s | 53 +++++++++++ src/xenia/cpu/ppc/testing/instr_stfs.s | 53 +++++++++++ src/xenia/cpu/ppc/testing/instr_sth.s | 53 +++++++++++ src/xenia/cpu/ppc/testing/instr_sthbrx.s | 71 +++++++++++++++ src/xenia/cpu/ppc/testing/instr_stmw.s | 25 ++++++ src/xenia/cpu/ppc/testing/instr_stvewx128.s | 43 +++++++++ src/xenia/cpu/ppc/testing/instr_stvlx128.s | 22 +++++ src/xenia/cpu/ppc/testing/instr_stvlxl128.s | 22 +++++ src/xenia/cpu/ppc/testing/instr_stvrx128.s | 21 +++++ src/xenia/cpu/ppc/testing/instr_stvrxl128.s | 21 +++++ src/xenia/cpu/ppc/testing/instr_stvx.s | 40 +++++++++ src/xenia/cpu/ppc/testing/instr_stvx128.s | 51 +++++++++++ src/xenia/cpu/ppc/testing/instr_stvxl.s | 26 ++++++ src/xenia/cpu/ppc/testing/instr_stvxl128.s | 26 ++++++ src/xenia/cpu/ppc/testing/instr_stw.s | 53 +++++++++++ src/xenia/cpu/ppc/testing/instr_stwbrx.s | 35 ++++++++ src/xenia/cpu/ppc/testing/instr_stwcx.s | 63 +++++++++++++ src/xenia/cpu/ppc/testing/instr_subfx.s | 90 +++++++++++++++++++ src/xenia/cpu/ppc/testing/instr_sync.s | 13 +++ src/xenia/cpu/ppc/testing/instr_vcfpsxws128.s | 63 +++++++++++++ src/xenia/cpu/ppc/testing/instr_vcfpuxws128.s | 63 +++++++++++++ src/xenia/cpu/ppc/testing/instr_vcmpequw128.s | 59 ++++++++++++ src/xenia/cpu/ppc/testing/instr_vcmpgefp128.s | 69 ++++++++++++++ src/xenia/cpu/ppc/testing/instr_vcmpgtfp128.s | 69 ++++++++++++++ src/xenia/cpu/ppc/testing/instr_vcsxwfp128.s | 63 +++++++++++++ src/xenia/cpu/ppc/testing/instr_vcuxwfp128.s | 63 +++++++++++++ src/xenia/cpu/ppc/testing/instr_vexptefp128.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_vlogefp128.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_vmaddcfp128.s | 32 +++++++ src/xenia/cpu/ppc/testing/instr_vmaddfp128.s | 54 +++++++++++ src/xenia/cpu/ppc/testing/instr_vmrghw128.s | 8 ++ src/xenia/cpu/ppc/testing/instr_vmrglw128.s | 8 ++ src/xenia/cpu/ppc/testing/instr_vmulfp128.s | 49 ++++++++++ src/xenia/cpu/ppc/testing/instr_vnmsubfp128.s | 54 +++++++++++ src/xenia/cpu/ppc/testing/instr_vnor128.s | 8 ++ src/xenia/cpu/ppc/testing/instr_vperm128.s | 21 +++++ src/xenia/cpu/ppc/testing/instr_vrefp128.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_vrfim128.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_vrfin128.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_vrfip128.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_vrfiz128.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_vrlw128.s | 8 ++ .../cpu/ppc/testing/instr_vrsqrtefp128.s | 39 ++++++++ src/xenia/cpu/ppc/testing/instr_vsel128.s | 10 +++ src/xenia/cpu/ppc/testing/instr_vsldoi128.s | 8 ++ src/xenia/cpu/ppc/testing/instr_vslo128.s | 8 ++ src/xenia/cpu/ppc/testing/instr_vslw128.s | 8 ++ src/xenia/cpu/ppc/testing/instr_vspltisw128.s | 11 +++ src/xenia/cpu/ppc/testing/instr_vspltw128.s | 13 +++ src/xenia/cpu/ppc/testing/instr_vsraw128.s | 8 ++ src/xenia/cpu/ppc/testing/instr_vsro128.s | 8 ++ src/xenia/cpu/ppc/testing/instr_vsrw128.s | 8 ++ 166 files changed, 5621 insertions(+) create mode 100644 src/xenia/cpu/ppc/testing/instr_addx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_cntlzdx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_cntlzwx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_dcbf.s create mode 100644 src/xenia/cpu/ppc/testing/instr_dcbst.s create mode 100644 src/xenia/cpu/ppc/testing/instr_dcbt.s create mode 100644 src/xenia/cpu/ppc/testing/instr_dcbtst.s create mode 100644 src/xenia/cpu/ppc/testing/instr_dcbz.s create mode 100644 src/xenia/cpu/ppc/testing/instr_dcbz128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_divdx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_eieio.s create mode 100644 src/xenia/cpu/ppc/testing/instr_eqvx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_extsbx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_extshx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_extswx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fabsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_faddsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_faddx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fcfidx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fcmpo.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fcmpu.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fctidx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fctidzx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fctiwx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fctiwzx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fdivsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fdivx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fmaddsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fmaddx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fmrx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fmsubsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fmsubx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fmulsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fmulx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fnabsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fnegx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fnmaddsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fnmaddx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fnmsubsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fnmsubx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fresx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_frspx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_frsqrtex.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fselx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fsqrtsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fsqrtx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fsubsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_fsubx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_icbi.s create mode 100644 src/xenia/cpu/ppc/testing/instr_isync.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lbz.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lbzu.s create mode 100644 src/xenia/cpu/ppc/testing/instr_ld.s create mode 100644 src/xenia/cpu/ppc/testing/instr_ldu.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lfd.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lfs.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lha.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lhau.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lhbrx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lhz.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lhzu.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lmw.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lvlx128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lvlxl128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lvrx128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lvrxl128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lvsl128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lvsr128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lvxl128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lwa.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lwbrx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lwz.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lwzu.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lxarx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_lxbrx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mcrfs.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mcrxr.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mffsx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mfmsr.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mfspr.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mftb.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mfvscr.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mtcrf.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mtfsfix.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mtfsfx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mtmsr.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mtmsrd.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mtspr.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mulhdux.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mulhdx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mulhwux.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mulhwx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_mulldx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_negx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_orcx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_rldclx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_rldcrx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_rldiclx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_rldicrx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_rldicx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_rldimix.s create mode 100644 src/xenia/cpu/ppc/testing/instr_rlwimix.s create mode 100644 src/xenia/cpu/ppc/testing/instr_rlwinmx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_rlwnmx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_sldx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_slwx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_sradix.s create mode 100644 src/xenia/cpu/ppc/testing/instr_sradx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_srawix.s create mode 100644 src/xenia/cpu/ppc/testing/instr_srawx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_srdx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_srwx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stb.s create mode 100644 src/xenia/cpu/ppc/testing/instr_std.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stfd.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stfs.s create mode 100644 src/xenia/cpu/ppc/testing/instr_sth.s create mode 100644 src/xenia/cpu/ppc/testing/instr_sthbrx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stmw.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stvewx128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stvlx128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stvlxl128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stvrx128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stvrxl128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stvx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stvx128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stvxl.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stvxl128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stw.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stwbrx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_stwcx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_subfx.s create mode 100644 src/xenia/cpu/ppc/testing/instr_sync.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vcfpsxws128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vcfpuxws128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vcmpequw128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vcmpgefp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vcmpgtfp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vcsxwfp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vcuxwfp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vexptefp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vlogefp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vmaddcfp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vmaddfp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vmrghw128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vmrglw128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vmulfp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vnmsubfp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vnor128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vperm128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrefp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrfim128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrfin128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrfip128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrfiz128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrlw128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vrsqrtefp128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vsel128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vsldoi128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vslo128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vslw128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vspltisw128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vspltw128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vsraw128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vsro128.s create mode 100644 src/xenia/cpu/ppc/testing/instr_vsrw128.s diff --git a/src/xenia/cpu/ppc/testing/instr_addx.s b/src/xenia/cpu/ppc/testing/instr_addx.s new file mode 100644 index 000000000..6d6881269 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_addx.s @@ -0,0 +1,90 @@ +test_addx_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000002000 + add. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000003000 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_addx_1_constant: + li r4, 0x1000 + li r5, 0x2000 + add. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000003000 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_addx_overflow: + #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000001 + add. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r12 0x0000000020000000 + +test_addx_negative: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000001 + add. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r12 0x0000000020000000 + +test_addcx_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000002000 + addc. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000003000 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_addcx_overflow: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000001 + addc. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r12 0x0000000020000000 + +test_addex_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000002000 + #_ REGISTER_IN r0 0x0000000020000000 + mtxer r0 + adde. r3, r4, r5 + mfcr r12 + mfxer r6 + blr + #_ REGISTER_OUT r3 0x0000000000003001 + #_ REGISTER_OUT r6 0x0000000000000000 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_addmex_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r0 0x0000000000000000 + mtxer r0 + addme. r3, r4 + mfcr r12 + mfxer r6 + blr + #_ REGISTER_OUT r3 0x0000000000000FFF + #_ REGISTER_OUT r6 0x0000000020000000 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_addzex_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r0 0x0000000000000000 + mtxer r0 + addze. r3, r4 + mfcr r12 + mfxer r6 + blr + #_ REGISTER_OUT r3 0x0000000000001000 + #_ REGISTER_OUT r6 0x0000000000000000 + #_ REGISTER_OUT r12 0x0000000040000000 diff --git a/src/xenia/cpu/ppc/testing/instr_cntlzdx.s b/src/xenia/cpu/ppc/testing/instr_cntlzdx.s new file mode 100644 index 000000000..4533e3b1e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_cntlzdx.s @@ -0,0 +1,27 @@ +test_cntlzdx_1: + #_ REGISTER_IN r4 0x0000000000000001 + cntlzd. r3, r4 + blr + #_ REGISTER_OUT r3 0x000000000000003F + #_ REGISTER_OUT r4 0x0000000000000001 + +test_cntlzdx_2: + #_ REGISTER_IN r4 0x8000000000000000 + cntlzd. r3, r4 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x8000000000000000 + +test_cntlzdx_3: + #_ REGISTER_IN r4 0x0000000000000000 + cntlzd. r3, r4 + blr + #_ REGISTER_OUT r3 0x0000000000000040 + #_ REGISTER_OUT r4 0x0000000000000000 + +test_cntlzdx_4: + #_ REGISTER_IN r4 0x0000000100000000 + cntlzd. r3, r4 + blr + #_ REGISTER_OUT r3 0x000000000000001F + #_ REGISTER_OUT r4 0x0000000100000000 diff --git a/src/xenia/cpu/ppc/testing/instr_cntlzwx.s b/src/xenia/cpu/ppc/testing/instr_cntlzwx.s new file mode 100644 index 000000000..7b0fe124c --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_cntlzwx.s @@ -0,0 +1,27 @@ +test_cntlzwx_1: + #_ REGISTER_IN r4 0x0000000000000001 + cntlzw. r3, r4 + blr + #_ REGISTER_OUT r3 0x000000000000001F + #_ REGISTER_OUT r4 0x0000000000000001 + +test_cntlzwx_2: + #_ REGISTER_IN r4 0x0000000080000000 + cntlzw. r3, r4 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000080000000 + +test_cntlzwx_3: + #_ REGISTER_IN r4 0x0000000000000000 + cntlzw. r3, r4 + blr + #_ REGISTER_OUT r3 0x0000000000000020 + #_ REGISTER_OUT r4 0x0000000000000000 + +test_cntlzwx_4: + #_ REGISTER_IN r4 0x0000000000010000 + cntlzw. r3, r4 + blr + #_ REGISTER_OUT r3 0x000000000000000F + #_ REGISTER_OUT r4 0x0000000000010000 diff --git a/src/xenia/cpu/ppc/testing/instr_dcbf.s b/src/xenia/cpu/ppc/testing/instr_dcbf.s new file mode 100644 index 000000000..e08226c37 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_dcbf.s @@ -0,0 +1,31 @@ +test_dcbf_1: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 0 + dcbf r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 0 + +test_dcbf_2: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 64 + dcbf r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 64 + +test_dcbf_3: + #_ REGISTER_IN r4 0 + #_ REGISTER_IN r5 0x00001000 + dcbf r4, r5 + blr + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 0x00001000 + +test_dcbf_4: + #_ REGISTER_IN r4 0x00002000 + #_ REGISTER_IN r5 128 + dcbf r4, r5 + blr + #_ REGISTER_OUT r4 0x00002000 + #_ REGISTER_OUT r5 128 diff --git a/src/xenia/cpu/ppc/testing/instr_dcbst.s b/src/xenia/cpu/ppc/testing/instr_dcbst.s new file mode 100644 index 000000000..613c450d2 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_dcbst.s @@ -0,0 +1,31 @@ +test_dcbst_1: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 0 + dcbst r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 0 + +test_dcbst_2: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 64 + dcbst r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 64 + +test_dcbst_3: + #_ REGISTER_IN r4 0 + #_ REGISTER_IN r5 0x00001000 + dcbst r4, r5 + blr + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 0x00001000 + +test_dcbst_4: + #_ REGISTER_IN r4 0x00002000 + #_ REGISTER_IN r5 128 + dcbst r4, r5 + blr + #_ REGISTER_OUT r4 0x00002000 + #_ REGISTER_OUT r5 128 diff --git a/src/xenia/cpu/ppc/testing/instr_dcbt.s b/src/xenia/cpu/ppc/testing/instr_dcbt.s new file mode 100644 index 000000000..bdc59d703 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_dcbt.s @@ -0,0 +1,31 @@ +test_dcbt_1: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 0 + dcbt r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 0 + +test_dcbt_2: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 64 + dcbt r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 64 + +test_dcbt_3: + #_ REGISTER_IN r4 0 + #_ REGISTER_IN r5 0x00001000 + dcbt r4, r5 + blr + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 0x00001000 + +test_dcbt_4: + #_ REGISTER_IN r4 0x00002000 + #_ REGISTER_IN r5 128 + dcbt r4, r5 + blr + #_ REGISTER_OUT r4 0x00002000 + #_ REGISTER_OUT r5 128 diff --git a/src/xenia/cpu/ppc/testing/instr_dcbtst.s b/src/xenia/cpu/ppc/testing/instr_dcbtst.s new file mode 100644 index 000000000..1c3474fed --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_dcbtst.s @@ -0,0 +1,31 @@ +test_dcbtst_1: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 0 + dcbtst r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 0 + +test_dcbtst_2: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 64 + dcbtst r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 64 + +test_dcbtst_3: + #_ REGISTER_IN r4 0 + #_ REGISTER_IN r5 0x00001000 + dcbtst r4, r5 + blr + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 0x00001000 + +test_dcbtst_4: + #_ REGISTER_IN r4 0x00002000 + #_ REGISTER_IN r5 128 + dcbtst r4, r5 + blr + #_ REGISTER_OUT r4 0x00002000 + #_ REGISTER_OUT r5 128 diff --git a/src/xenia/cpu/ppc/testing/instr_dcbz.s b/src/xenia/cpu/ppc/testing/instr_dcbz.s new file mode 100644 index 000000000..40c59d7b1 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_dcbz.s @@ -0,0 +1,39 @@ +test_dcbz_1: + #_ MEMORY_IN 0x0000000010001000 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0 + dcbz r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0 + #_ MEMORY_OUT 10001000 00000000000000000000000000000000000000000000000000000000000000 + +test_dcbz_2: + #_ MEMORY_IN 0x0000000010001040 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 64 + dcbz r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 64 + #_ MEMORY_OUT 10001040 00000000000000000000000000000000000000000000000000000000000000 + +test_dcbz_3: + #_ MEMORY_IN 0x0000000010001000 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF] + #_ REGISTER_IN r4 0 + #_ REGISTER_IN r5 0x0000000010001000 + dcbz r4, r5 + blr + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 0x0000000010001000 + #_ MEMORY_OUT 10001000 00000000000000000000000000000000000000000000000000000000000000 + +test_dcbz_4: + #_ MEMORY_IN 0x0000000010001080 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 128 + dcbz r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 128 + #_ MEMORY_OUT 10001080 00000000000000000000000000000000000000000000000000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_dcbz128.s b/src/xenia/cpu/ppc/testing/instr_dcbz128.s new file mode 100644 index 000000000..b69aca25e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_dcbz128.s @@ -0,0 +1,28 @@ +test_dcbz128_1: + # Clear 128 bytes starting at aligned address + #_ MEMORY_IN 10001000 0102030405060708090A0B0C0D0E0F10111213141516171819191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F80 + li r4, 0x1000 + oris r4, r4, 0x1000 + dcbz128 r0, r4 + blr + #_ MEMORY_OUT 10001000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + +test_dcbz128_2: + # Clear 128 bytes with non-zero base register + #_ MEMORY_IN 10002000 0102030405060708090A0B0C0D0E0F10111213141516171819191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F80 + li r3, 0x1000 + oris r3, r3, 0x1000 + li r4, 0x1000 + dcbz128 r3, r4 + blr + #_ MEMORY_OUT 10002000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + +test_dcbz128_3: + # Verify unaligned address is rounded down to 128-byte boundary + # Address 10003040 should clear block starting at 10003000 + #_ MEMORY_IN 10003000 0102030405060708090A0B0C0D0E0F10111213141516171819191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F80 + li r4, 0x3040 + oris r4, r4, 0x1000 + dcbz128 r0, r4 + blr + #_ MEMORY_OUT 10003000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_divdx.s b/src/xenia/cpu/ppc/testing/instr_divdx.s new file mode 100644 index 000000000..b1bc5baf5 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_divdx.s @@ -0,0 +1,89 @@ +test_divdx_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000000010 + divd. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000100 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_divdx_1_constant: + li r4, 0x1000 + li r5, 0x10 + divd. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000100 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_divdx_negative: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFF000 + #_ REGISTER_IN r5 0x0000000000000010 + divd. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF00 + #_ REGISTER_OUT r12 0x0000000080000000 + +test_divdx_by_zero: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000000000 + divd. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r12 0x0000000020000000 + +test_divdux_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000000010 + divdu. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000100 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_divdux_large: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000002 + divdu. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r12 0x0000000080000000 + +test_divwx_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000000010 + divw. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000100 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_divwx_negative: + #_ REGISTER_IN r4 0x00000000FFFFF000 + #_ REGISTER_IN r5 0x0000000000000010 + divw. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFF00 + #_ REGISTER_OUT r12 0x0000000080000000 + +test_divwux_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000000010 + divwu. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000100 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_divwux_large: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x0000000000000002 + divwu. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x000000007FFFFFFF + #_ REGISTER_OUT r12 0x0000000040000000 diff --git a/src/xenia/cpu/ppc/testing/instr_eieio.s b/src/xenia/cpu/ppc/testing/instr_eieio.s new file mode 100644 index 000000000..48c37dacb --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_eieio.s @@ -0,0 +1,13 @@ +test_eieio_1: + #_ REGISTER_IN r3 0x0000000000000001 + eieio + blr + #_ REGISTER_OUT r3 0x0000000000000001 + +test_eieio_2: + #_ REGISTER_IN r4 0x0000000012345678 + #_ REGISTER_IN r5 0xABCDEF0123456789 + eieio + blr + #_ REGISTER_OUT r4 0x0000000012345678 + #_ REGISTER_OUT r5 0xABCDEF0123456789 diff --git a/src/xenia/cpu/ppc/testing/instr_eqvx.s b/src/xenia/cpu/ppc/testing/instr_eqvx.s new file mode 100644 index 000000000..76c828251 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_eqvx.s @@ -0,0 +1,35 @@ +test_eqvx_1: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + eqv. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + +test_eqvx_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xAAAAAAAAAAAAAAAA + eqv. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xAAAAAAAAAAAAAAAA + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xAAAAAAAAAAAAAAAA + +test_eqvx_3: + #_ REGISTER_IN r4 0xAAAAAAAAAAAAAAAA + #_ REGISTER_IN r5 0x5555555555555555 + eqv. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0xAAAAAAAAAAAAAAAA + #_ REGISTER_OUT r5 0x5555555555555555 + +test_eqvx_4: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + #_ REGISTER_IN r5 0x123456789ABCDEF0 + eqv. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + #_ REGISTER_OUT r5 0x123456789ABCDEF0 diff --git a/src/xenia/cpu/ppc/testing/instr_extsbx.s b/src/xenia/cpu/ppc/testing/instr_extsbx.s new file mode 100644 index 000000000..6da00041e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_extsbx.s @@ -0,0 +1,27 @@ +test_extsbx_1: + #_ REGISTER_IN r4 0x000000000000007F + extsb. r3, r4 + blr + #_ REGISTER_OUT r3 0x000000000000007F + #_ REGISTER_OUT r4 0x000000000000007F + +test_extsbx_2: + #_ REGISTER_IN r4 0x0000000000000080 + extsb. r3, r4 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80 + #_ REGISTER_OUT r4 0x0000000000000080 + +test_extsbx_3: + #_ REGISTER_IN r4 0x00000000000000FF + extsb. r3, r4 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x00000000000000FF + +test_extsbx_4: + #_ REGISTER_IN r4 0x0000000000000001 + extsb. r3, r4 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_extshx.s b/src/xenia/cpu/ppc/testing/instr_extshx.s new file mode 100644 index 000000000..7d15f6ec0 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_extshx.s @@ -0,0 +1,27 @@ +test_extshx_1: + #_ REGISTER_IN r4 0x0000000000007FFF + extsh. r3, r4 + blr + #_ REGISTER_OUT r3 0x0000000000007FFF + #_ REGISTER_OUT r4 0x0000000000007FFF + +test_extshx_2: + #_ REGISTER_IN r4 0x0000000000008000 + extsh. r3, r4 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000 + #_ REGISTER_OUT r4 0x0000000000008000 + +test_extshx_3: + #_ REGISTER_IN r4 0x000000000000FFFF + extsh. r3, r4 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x000000000000FFFF + +test_extshx_4: + #_ REGISTER_IN r4 0x0000000000000001 + extsh. r3, r4 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_extswx.s b/src/xenia/cpu/ppc/testing/instr_extswx.s new file mode 100644 index 000000000..f50aaea70 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_extswx.s @@ -0,0 +1,27 @@ +test_extswx_1: + #_ REGISTER_IN r4 0x000000007FFFFFFF + extsw. r3, r4 + blr + #_ REGISTER_OUT r3 0x000000007FFFFFFF + #_ REGISTER_OUT r4 0x000000007FFFFFFF + +test_extswx_2: + #_ REGISTER_IN r4 0x0000000080000000 + extsw. r3, r4 + blr + #_ REGISTER_OUT r3 0xFFFFFFFF80000000 + #_ REGISTER_OUT r4 0x0000000080000000 + +test_extswx_3: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + extsw. r3, r4 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + +test_extswx_4: + #_ REGISTER_IN r4 0x0000000000000001 + extsw. r3, r4 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_fabsx.s b/src/xenia/cpu/ppc/testing/instr_fabsx.s new file mode 100644 index 000000000..c79745523 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fabsx.s @@ -0,0 +1,27 @@ +test_fabsx_1: + #_ REGISTER_IN f4 [3FF0000000000000] + fabs. f3, f4 + blr + #_ REGISTER_OUT f3 [3FF0000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + +test_fabsx_2: + #_ REGISTER_IN f4 [BFF0000000000000] + fabs. f3, f4 + blr + #_ REGISTER_OUT f3 [3FF0000000000000] + #_ REGISTER_OUT f4 [BFF0000000000000] + +test_fabsx_3: + #_ REGISTER_IN f4 [8000000000000000] + fabs. f3, f4 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [8000000000000000] + +test_fabsx_4: + #_ REGISTER_IN f4 [C005000000000000] + fabs. f3, f4 + blr + #_ REGISTER_OUT f3 [4005000000000000] + #_ REGISTER_OUT f4 [C005000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_faddsx.s b/src/xenia/cpu/ppc/testing/instr_faddsx.s new file mode 100644 index 000000000..944c1ad4c --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_faddsx.s @@ -0,0 +1,35 @@ +test_faddsx_1: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fadds. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4008000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [4000000000000000] + +test_faddsx_2: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [BFF0000000000000] + fadds. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [BFF0000000000000] + +test_faddsx_3: + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fadds. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4010000000000000] + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] + +test_faddsx_4: + #_ REGISTER_IN f4 [0000000000000000] + #_ REGISTER_IN f5 [0000000000000000] + fadds. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + #_ REGISTER_OUT f5 [0000000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_faddx.s b/src/xenia/cpu/ppc/testing/instr_faddx.s new file mode 100644 index 000000000..e86fe5e5e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_faddx.s @@ -0,0 +1,35 @@ +test_faddx_1: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fadd. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4008000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [4000000000000000] + +test_faddx_2: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [BFF0000000000000] + fadd. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [BFF0000000000000] + +test_faddx_3: + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fadd. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4010000000000000] + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] + +test_faddx_4: + #_ REGISTER_IN f4 [0000000000000000] + #_ REGISTER_IN f5 [0000000000000000] + fadd. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + #_ REGISTER_OUT f5 [0000000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fcfidx.s b/src/xenia/cpu/ppc/testing/instr_fcfidx.s new file mode 100644 index 000000000..9be79130a --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fcfidx.s @@ -0,0 +1,27 @@ +test_fcfidx_1: + #_ REGISTER_IN f1 0x0000000000000001 + fcfid. f3, f1 + blr + #_ REGISTER_OUT f3 1.0 + #_ REGISTER_OUT f1 0x0000000000000001 + +test_fcfidx_2: + #_ REGISTER_IN f1 0xFFFFFFFFFFFFFFFF + fcfid. f3, f1 + blr + #_ REGISTER_OUT f3 -1.0 + #_ REGISTER_OUT f1 0xFFFFFFFFFFFFFFFF + +test_fcfidx_3: + #_ REGISTER_IN f1 0x0000000000000064 + fcfid. f3, f1 + blr + #_ REGISTER_OUT f3 100.0 + #_ REGISTER_OUT f1 0x0000000000000064 + +test_fcfidx_4: + #_ REGISTER_IN f1 0x0000000000000000 + fcfid. f3, f1 + blr + #_ REGISTER_OUT f3 0.0 + #_ REGISTER_OUT f1 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_fcmpo.s b/src/xenia/cpu/ppc/testing/instr_fcmpo.s new file mode 100644 index 000000000..6369ecdd1 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fcmpo.s @@ -0,0 +1,39 @@ +test_fcmpo_1: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fcmpo cr0, f4, f5 + mfcr r3 + blr + #_ REGISTER_OUT r3 0x20000000 + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [4000000000000000] + +test_fcmpo_2: + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fcmpo cr0, f4, f5 + mfcr r3 + blr + #_ REGISTER_OUT r3 0x20000000 + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4000000000000000] + +test_fcmpo_3: + #_ REGISTER_IN f4 [4008000000000000] + #_ REGISTER_IN f5 [3FF0000000000000] + fcmpo cr0, f4, f5 + mfcr r3 + blr + #_ REGISTER_OUT r3 0x20000000 + #_ REGISTER_OUT f4 [4008000000000000] + #_ REGISTER_OUT f5 [3FF0000000000000] + +test_fcmpo_4: + #_ REGISTER_IN f4 [0000000000000000] + #_ REGISTER_IN f5 [0000000000000000] + fcmpo cr0, f4, f5 + mfcr r3 + blr + #_ REGISTER_OUT r3 0x20000000 + #_ REGISTER_OUT f4 [0000000000000000] + #_ REGISTER_OUT f5 [0000000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fcmpu.s b/src/xenia/cpu/ppc/testing/instr_fcmpu.s new file mode 100644 index 000000000..2a7fa5937 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fcmpu.s @@ -0,0 +1,39 @@ +test_fcmpu_1: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fcmpu cr0, f4, f5 + mfcr r3 + blr + #_ REGISTER_OUT r3 0x20000000 + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [4000000000000000] + +test_fcmpu_2: + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fcmpu cr0, f4, f5 + mfcr r3 + blr + #_ REGISTER_OUT r3 0x20000000 + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4000000000000000] + +test_fcmpu_3: + #_ REGISTER_IN f4 [4008000000000000] + #_ REGISTER_IN f5 [3FF0000000000000] + fcmpu cr0, f4, f5 + mfcr r3 + blr + #_ REGISTER_OUT r3 0x20000000 + #_ REGISTER_OUT f4 [4008000000000000] + #_ REGISTER_OUT f5 [3FF0000000000000] + +test_fcmpu_4: + #_ REGISTER_IN f4 [0000000000000000] + #_ REGISTER_IN f5 [0000000000000000] + fcmpu cr0, f4, f5 + mfcr r3 + blr + #_ REGISTER_OUT r3 0x20000000 + #_ REGISTER_OUT f4 [0000000000000000] + #_ REGISTER_OUT f5 [0000000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fctidx.s b/src/xenia/cpu/ppc/testing/instr_fctidx.s new file mode 100644 index 000000000..481236dac --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fctidx.s @@ -0,0 +1,27 @@ +test_fctidx_1: + #_ REGISTER_IN f1 3.7 + fctid. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000004 + #_ REGISTER_OUT f1 3.7 + +test_fctidx_2: + #_ REGISTER_IN f1 -2.3 + fctid. f3, f1 + blr + #_ REGISTER_OUT f3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT f1 -2.3 + +test_fctidx_3: + #_ REGISTER_IN f1 100.9 + fctid. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000065 + #_ REGISTER_OUT f1 100.9 + +test_fctidx_4: + #_ REGISTER_IN f1 0.0 + fctid. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000000 + #_ REGISTER_OUT f1 0.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fctidzx.s b/src/xenia/cpu/ppc/testing/instr_fctidzx.s new file mode 100644 index 000000000..3df7a444a --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fctidzx.s @@ -0,0 +1,27 @@ +test_fctidzx_1: + #_ REGISTER_IN f1 3.7 + fctidz. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000003 + #_ REGISTER_OUT f1 3.7 + +test_fctidzx_2: + #_ REGISTER_IN f1 -2.9 + fctidz. f3, f1 + blr + #_ REGISTER_OUT f3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT f1 -2.9 + +test_fctidzx_3: + #_ REGISTER_IN f1 100.1 + fctidz. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000064 + #_ REGISTER_OUT f1 100.1 + +test_fctidzx_4: + #_ REGISTER_IN f1 -0.5 + fctidz. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000000 + #_ REGISTER_OUT f1 -0.5 diff --git a/src/xenia/cpu/ppc/testing/instr_fctiwx.s b/src/xenia/cpu/ppc/testing/instr_fctiwx.s new file mode 100644 index 000000000..8694a8591 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fctiwx.s @@ -0,0 +1,27 @@ +test_fctiwx_1: + #_ REGISTER_IN f1 3.7 + fctiw. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000004 + #_ REGISTER_OUT f1 3.7 + +test_fctiwx_2: + #_ REGISTER_IN f1 -2.3 + fctiw. f3, f1 + blr + #_ REGISTER_OUT f3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT f1 -2.3 + +test_fctiwx_3: + #_ REGISTER_IN f1 100.9 + fctiw. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000065 + #_ REGISTER_OUT f1 100.9 + +test_fctiwx_4: + #_ REGISTER_IN f1 0.0 + fctiw. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000000 + #_ REGISTER_OUT f1 0.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fctiwzx.s b/src/xenia/cpu/ppc/testing/instr_fctiwzx.s new file mode 100644 index 000000000..562fe705b --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fctiwzx.s @@ -0,0 +1,27 @@ +test_fctiwzx_1: + #_ REGISTER_IN f1 3.7 + fctiwz. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000003 + #_ REGISTER_OUT f1 3.7 + +test_fctiwzx_2: + #_ REGISTER_IN f1 -2.9 + fctiwz. f3, f1 + blr + #_ REGISTER_OUT f3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT f1 -2.9 + +test_fctiwzx_3: + #_ REGISTER_IN f1 100.1 + fctiwz. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000064 + #_ REGISTER_OUT f1 100.1 + +test_fctiwzx_4: + #_ REGISTER_IN f1 -0.5 + fctiwz. f3, f1 + blr + #_ REGISTER_OUT f3 0x0000000000000000 + #_ REGISTER_OUT f1 -0.5 diff --git a/src/xenia/cpu/ppc/testing/instr_fdivsx.s b/src/xenia/cpu/ppc/testing/instr_fdivsx.s new file mode 100644 index 000000000..c4676e79e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fdivsx.s @@ -0,0 +1,35 @@ +test_fdivsx_1: + #_ REGISTER_IN f1 6.0 + #_ REGISTER_IN f2 2.0 + fdivs. f3, f1, f2 + blr + #_ REGISTER_OUT f3 3.0 + #_ REGISTER_OUT f1 6.0 + #_ REGISTER_OUT f2 2.0 + +test_fdivsx_2: + #_ REGISTER_IN f1 1.0 + #_ REGISTER_IN f2 -1.0 + fdivs. f3, f1, f2 + blr + #_ REGISTER_OUT f3 -1.0 + #_ REGISTER_OUT f1 1.0 + #_ REGISTER_OUT f2 -1.0 + +test_fdivsx_3: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 2.0 + fdivs. f3, f1, f2 + blr + #_ REGISTER_OUT f3 1.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 2.0 + +test_fdivsx_4: + #_ REGISTER_IN f1 4.0 + #_ REGISTER_IN f2 2.0 + fdivs. f3, f1, f2 + blr + #_ REGISTER_OUT f3 2.0 + #_ REGISTER_OUT f1 4.0 + #_ REGISTER_OUT f2 2.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fdivx.s b/src/xenia/cpu/ppc/testing/instr_fdivx.s new file mode 100644 index 000000000..13c7e59be --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fdivx.s @@ -0,0 +1,35 @@ +test_fdivx_1: + #_ REGISTER_IN f1 6.0 + #_ REGISTER_IN f2 2.0 + fdiv. f3, f1, f2 + blr + #_ REGISTER_OUT f3 3.0 + #_ REGISTER_OUT f1 6.0 + #_ REGISTER_OUT f2 2.0 + +test_fdivx_2: + #_ REGISTER_IN f1 1.0 + #_ REGISTER_IN f2 -1.0 + fdiv. f3, f1, f2 + blr + #_ REGISTER_OUT f3 -1.0 + #_ REGISTER_OUT f1 1.0 + #_ REGISTER_OUT f2 -1.0 + +test_fdivx_3: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 2.0 + fdiv. f3, f1, f2 + blr + #_ REGISTER_OUT f3 1.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 2.0 + +test_fdivx_4: + #_ REGISTER_IN f1 4.0 + #_ REGISTER_IN f2 2.0 + fdiv. f3, f1, f2 + blr + #_ REGISTER_OUT f3 2.0 + #_ REGISTER_OUT f1 4.0 + #_ REGISTER_OUT f2 2.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fmaddsx.s b/src/xenia/cpu/ppc/testing/instr_fmaddsx.s new file mode 100644 index 000000000..5e6d27e48 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fmaddsx.s @@ -0,0 +1,43 @@ +test_fmaddsx_1: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 3.0 + #_ REGISTER_IN f3 4.0 + fmadds. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 10.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 3.0 + #_ REGISTER_OUT f3 4.0 + +test_fmaddsx_2: + #_ REGISTER_IN f1 -1.5 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 1.0 + fmadds. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -2.0 + #_ REGISTER_OUT f1 -1.5 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 1.0 + +test_fmaddsx_3: + #_ REGISTER_IN f1 0.5 + #_ REGISTER_IN f2 0.5 + #_ REGISTER_IN f3 0.25 + fmadds. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 0.5 + #_ REGISTER_OUT f1 0.5 + #_ REGISTER_OUT f2 0.5 + #_ REGISTER_OUT f3 0.25 + +test_fmaddsx_4: + #_ REGISTER_IN f1 0.0 + #_ REGISTER_IN f2 100.0 + #_ REGISTER_IN f3 5.0 + fmadds. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 5.0 + #_ REGISTER_OUT f1 0.0 + #_ REGISTER_OUT f2 100.0 + #_ REGISTER_OUT f3 5.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fmaddx.s b/src/xenia/cpu/ppc/testing/instr_fmaddx.s new file mode 100644 index 000000000..ac5adb188 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fmaddx.s @@ -0,0 +1,43 @@ +test_fmaddx_1: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 3.0 + #_ REGISTER_IN f3 4.0 + fmadd. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 10.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 3.0 + #_ REGISTER_OUT f3 4.0 + +test_fmaddx_2: + #_ REGISTER_IN f1 -1.5 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 1.0 + fmadd. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -2.0 + #_ REGISTER_OUT f1 -1.5 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 1.0 + +test_fmaddx_3: + #_ REGISTER_IN f1 0.5 + #_ REGISTER_IN f2 0.5 + #_ REGISTER_IN f3 0.25 + fmadd. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 0.5 + #_ REGISTER_OUT f1 0.5 + #_ REGISTER_OUT f2 0.5 + #_ REGISTER_OUT f3 0.25 + +test_fmaddx_4: + #_ REGISTER_IN f1 0.0 + #_ REGISTER_IN f2 100.0 + #_ REGISTER_IN f3 5.0 + fmadd. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 5.0 + #_ REGISTER_OUT f1 0.0 + #_ REGISTER_OUT f2 100.0 + #_ REGISTER_OUT f3 5.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fmrx.s b/src/xenia/cpu/ppc/testing/instr_fmrx.s new file mode 100644 index 000000000..132aacb33 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fmrx.s @@ -0,0 +1,27 @@ +test_fmrx_1: + #_ REGISTER_IN f4 [3FF0000000000000] + fmr. f3, f4 + blr + #_ REGISTER_OUT f3 [3FF0000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + +test_fmrx_2: + #_ REGISTER_IN f4 [BFF0000000000000] + fmr. f3, f4 + blr + #_ REGISTER_OUT f3 [BFF0000000000000] + #_ REGISTER_OUT f4 [BFF0000000000000] + +test_fmrx_3: + #_ REGISTER_IN f4 [0000000000000000] + fmr. f3, f4 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + +test_fmrx_4: + #_ REGISTER_IN f4 [4005000000000000] + fmr. f3, f4 + blr + #_ REGISTER_OUT f3 [4005000000000000] + #_ REGISTER_OUT f4 [4005000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fmsubsx.s b/src/xenia/cpu/ppc/testing/instr_fmsubsx.s new file mode 100644 index 000000000..e59d8d44e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fmsubsx.s @@ -0,0 +1,43 @@ +test_fmsubsx_1: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 3.0 + #_ REGISTER_IN f3 4.0 + fmsubs. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 2.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 3.0 + #_ REGISTER_OUT f3 4.0 + +test_fmsubsx_2: + #_ REGISTER_IN f1 -1.5 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 1.0 + fmsubs. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -4.0 + #_ REGISTER_OUT f1 -1.5 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 1.0 + +test_fmsubsx_3: + #_ REGISTER_IN f1 0.5 + #_ REGISTER_IN f2 0.5 + #_ REGISTER_IN f3 0.25 + fmsubs. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 0.0 + #_ REGISTER_OUT f1 0.5 + #_ REGISTER_OUT f2 0.5 + #_ REGISTER_OUT f3 0.25 + +test_fmsubsx_4: + #_ REGISTER_IN f1 10.0 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 5.0 + fmsubs. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 15.0 + #_ REGISTER_OUT f1 10.0 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 5.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fmsubx.s b/src/xenia/cpu/ppc/testing/instr_fmsubx.s new file mode 100644 index 000000000..84b61b18d --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fmsubx.s @@ -0,0 +1,43 @@ +test_fmsubx_1: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 3.0 + #_ REGISTER_IN f3 4.0 + fmsub. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 2.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 3.0 + #_ REGISTER_OUT f3 4.0 + +test_fmsubx_2: + #_ REGISTER_IN f1 -1.5 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 1.0 + fmsub. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -4.0 + #_ REGISTER_OUT f1 -1.5 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 1.0 + +test_fmsubx_3: + #_ REGISTER_IN f1 0.5 + #_ REGISTER_IN f2 0.5 + #_ REGISTER_IN f3 0.25 + fmsub. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 0.0 + #_ REGISTER_OUT f1 0.5 + #_ REGISTER_OUT f2 0.5 + #_ REGISTER_OUT f3 0.25 + +test_fmsubx_4: + #_ REGISTER_IN f1 10.0 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 5.0 + fmsub. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 15.0 + #_ REGISTER_OUT f1 10.0 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 5.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fmulsx.s b/src/xenia/cpu/ppc/testing/instr_fmulsx.s new file mode 100644 index 000000000..d5580b8b0 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fmulsx.s @@ -0,0 +1,35 @@ +test_fmulsx_1: + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fmuls. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4018000000000000] + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] + +test_fmulsx_2: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [BFF0000000000000] + fmuls. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [BFF0000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [BFF0000000000000] + +test_fmulsx_3: + #_ REGISTER_IN f4 [0000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fmuls. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] + +test_fmulsx_4: + #_ REGISTER_IN f4 [3FE0000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fmuls. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [3FF0000000000000] + #_ REGISTER_OUT f4 [3FE0000000000000] + #_ REGISTER_OUT f5 [4000000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fmulx.s b/src/xenia/cpu/ppc/testing/instr_fmulx.s new file mode 100644 index 000000000..9a8b90e28 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fmulx.s @@ -0,0 +1,35 @@ +test_fmulx_1: + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fmul. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4018000000000000] + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] + +test_fmulx_2: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [BFF0000000000000] + fmul. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [BFF0000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [BFF0000000000000] + +test_fmulx_3: + #_ REGISTER_IN f4 [0000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fmul. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] + +test_fmulx_4: + #_ REGISTER_IN f4 [3FE0000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fmul. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [3FF0000000000000] + #_ REGISTER_OUT f4 [3FE0000000000000] + #_ REGISTER_OUT f5 [4000000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fnabsx.s b/src/xenia/cpu/ppc/testing/instr_fnabsx.s new file mode 100644 index 000000000..a832ebb89 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fnabsx.s @@ -0,0 +1,27 @@ +test_fnabsx_1: + #_ REGISTER_IN f4 [3FF0000000000000] + fnabs. f3, f4 + blr + #_ REGISTER_OUT f3 [BFF0000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + +test_fnabsx_2: + #_ REGISTER_IN f4 [BFF0000000000000] + fnabs. f3, f4 + blr + #_ REGISTER_OUT f3 [BFF0000000000000] + #_ REGISTER_OUT f4 [BFF0000000000000] + +test_fnabsx_3: + #_ REGISTER_IN f4 [0000000000000000] + fnabs. f3, f4 + blr + #_ REGISTER_OUT f3 [8000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + +test_fnabsx_4: + #_ REGISTER_IN f4 [4005000000000000] + fnabs. f3, f4 + blr + #_ REGISTER_OUT f3 [C005000000000000] + #_ REGISTER_OUT f4 [4005000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fnegx.s b/src/xenia/cpu/ppc/testing/instr_fnegx.s new file mode 100644 index 000000000..d7cac617e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fnegx.s @@ -0,0 +1,27 @@ +test_fnegx_1: + #_ REGISTER_IN f4 [3FF0000000000000] + fneg. f3, f4 + blr + #_ REGISTER_OUT f3 [BFF0000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + +test_fnegx_2: + #_ REGISTER_IN f4 [BFF0000000000000] + fneg. f3, f4 + blr + #_ REGISTER_OUT f3 [3FF0000000000000] + #_ REGISTER_OUT f4 [BFF0000000000000] + +test_fnegx_3: + #_ REGISTER_IN f4 [0000000000000000] + fneg. f3, f4 + blr + #_ REGISTER_OUT f3 [8000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + +test_fnegx_4: + #_ REGISTER_IN f4 [4005000000000000] + fneg. f3, f4 + blr + #_ REGISTER_OUT f3 [C005000000000000] + #_ REGISTER_OUT f4 [4005000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fnmaddsx.s b/src/xenia/cpu/ppc/testing/instr_fnmaddsx.s new file mode 100644 index 000000000..c3f4f3cd7 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fnmaddsx.s @@ -0,0 +1,43 @@ +test_fnmaddsx_1: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 3.0 + #_ REGISTER_IN f3 4.0 + fnmadds. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -10.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 3.0 + #_ REGISTER_OUT f3 4.0 + +test_fnmaddsx_2: + #_ REGISTER_IN f1 -1.5 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 1.0 + fnmadds. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 2.0 + #_ REGISTER_OUT f1 -1.5 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 1.0 + +test_fnmaddsx_3: + #_ REGISTER_IN f1 0.5 + #_ REGISTER_IN f2 0.5 + #_ REGISTER_IN f3 0.25 + fnmadds. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -0.5 + #_ REGISTER_OUT f1 0.5 + #_ REGISTER_OUT f2 0.5 + #_ REGISTER_OUT f3 0.25 + +test_fnmaddsx_4: + #_ REGISTER_IN f1 0.0 + #_ REGISTER_IN f2 100.0 + #_ REGISTER_IN f3 5.0 + fnmadds. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -5.0 + #_ REGISTER_OUT f1 0.0 + #_ REGISTER_OUT f2 100.0 + #_ REGISTER_OUT f3 5.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fnmaddx.s b/src/xenia/cpu/ppc/testing/instr_fnmaddx.s new file mode 100644 index 000000000..b94f0f871 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fnmaddx.s @@ -0,0 +1,43 @@ +test_fnmaddx_1: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 3.0 + #_ REGISTER_IN f3 4.0 + fnmadd. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -10.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 3.0 + #_ REGISTER_OUT f3 4.0 + +test_fnmaddx_2: + #_ REGISTER_IN f1 -1.5 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 1.0 + fnmadd. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 2.0 + #_ REGISTER_OUT f1 -1.5 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 1.0 + +test_fnmaddx_3: + #_ REGISTER_IN f1 0.5 + #_ REGISTER_IN f2 0.5 + #_ REGISTER_IN f3 0.25 + fnmadd. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -0.5 + #_ REGISTER_OUT f1 0.5 + #_ REGISTER_OUT f2 0.5 + #_ REGISTER_OUT f3 0.25 + +test_fnmaddx_4: + #_ REGISTER_IN f1 0.0 + #_ REGISTER_IN f2 100.0 + #_ REGISTER_IN f3 5.0 + fnmadd. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -5.0 + #_ REGISTER_OUT f1 0.0 + #_ REGISTER_OUT f2 100.0 + #_ REGISTER_OUT f3 5.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fnmsubsx.s b/src/xenia/cpu/ppc/testing/instr_fnmsubsx.s new file mode 100644 index 000000000..5b5740b6c --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fnmsubsx.s @@ -0,0 +1,43 @@ +test_fnmsubsx_1: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 3.0 + #_ REGISTER_IN f3 4.0 + fnmsubs. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -2.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 3.0 + #_ REGISTER_OUT f3 4.0 + +test_fnmsubsx_2: + #_ REGISTER_IN f1 -1.5 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 1.0 + fnmsubs. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 4.0 + #_ REGISTER_OUT f1 -1.5 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 1.0 + +test_fnmsubsx_3: + #_ REGISTER_IN f1 0.5 + #_ REGISTER_IN f2 0.5 + #_ REGISTER_IN f3 0.25 + fnmsubs. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 0.0 + #_ REGISTER_OUT f1 0.5 + #_ REGISTER_OUT f2 0.5 + #_ REGISTER_OUT f3 0.25 + +test_fnmsubsx_4: + #_ REGISTER_IN f1 10.0 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 5.0 + fnmsubs. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -15.0 + #_ REGISTER_OUT f1 10.0 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 5.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fnmsubx.s b/src/xenia/cpu/ppc/testing/instr_fnmsubx.s new file mode 100644 index 000000000..daf1a5a52 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fnmsubx.s @@ -0,0 +1,43 @@ +test_fnmsubx_1: + #_ REGISTER_IN f1 2.0 + #_ REGISTER_IN f2 3.0 + #_ REGISTER_IN f3 4.0 + fnmsub. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -2.0 + #_ REGISTER_OUT f1 2.0 + #_ REGISTER_OUT f2 3.0 + #_ REGISTER_OUT f3 4.0 + +test_fnmsubx_2: + #_ REGISTER_IN f1 -1.5 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 1.0 + fnmsub. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 4.0 + #_ REGISTER_OUT f1 -1.5 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 1.0 + +test_fnmsubx_3: + #_ REGISTER_IN f1 0.5 + #_ REGISTER_IN f2 0.5 + #_ REGISTER_IN f3 0.25 + fnmsub. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 0.0 + #_ REGISTER_OUT f1 0.5 + #_ REGISTER_OUT f2 0.5 + #_ REGISTER_OUT f3 0.25 + +test_fnmsubx_4: + #_ REGISTER_IN f1 10.0 + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 5.0 + fnmsub. f5, f1, f2, f3 + blr + #_ REGISTER_OUT f5 -15.0 + #_ REGISTER_OUT f1 10.0 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 5.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fresx.s b/src/xenia/cpu/ppc/testing/instr_fresx.s new file mode 100644 index 000000000..75f9a65fc --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fresx.s @@ -0,0 +1,27 @@ +test_fresx_1: + #_ REGISTER_IN f1 2.0 + fres. f3, f1 + blr + #_ REGISTER_OUT f3 0.5 + #_ REGISTER_OUT f1 2.0 + +test_fresx_2: + #_ REGISTER_IN f1 4.0 + fres. f3, f1 + blr + #_ REGISTER_OUT f3 0.25 + #_ REGISTER_OUT f1 4.0 + +test_fresx_3: + #_ REGISTER_IN f1 0.5 + fres. f3, f1 + blr + #_ REGISTER_OUT f3 2.0 + #_ REGISTER_OUT f1 0.5 + +test_fresx_4: + #_ REGISTER_IN f1 1.0 + fres. f3, f1 + blr + #_ REGISTER_OUT f3 1.0 + #_ REGISTER_OUT f1 1.0 diff --git a/src/xenia/cpu/ppc/testing/instr_frspx.s b/src/xenia/cpu/ppc/testing/instr_frspx.s new file mode 100644 index 000000000..8c7bf68ce --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_frspx.s @@ -0,0 +1,27 @@ +test_frspx_1: + #_ REGISTER_IN f4 [3FF0000000000000] + frsp. f3, f4 + blr + #_ REGISTER_OUT f3 [3FF0000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + +test_frspx_2: + #_ REGISTER_IN f4 [4000000000000000] + frsp. f3, f4 + blr + #_ REGISTER_OUT f3 [4000000000000000] + #_ REGISTER_OUT f4 [4000000000000000] + +test_frspx_3: + #_ REGISTER_IN f4 [0000000000000000] + frsp. f3, f4 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + +test_frspx_4: + #_ REGISTER_IN f4 [4008000000000000] + frsp. f3, f4 + blr + #_ REGISTER_OUT f3 [4008000000000000] + #_ REGISTER_OUT f4 [4008000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_frsqrtex.s b/src/xenia/cpu/ppc/testing/instr_frsqrtex.s new file mode 100644 index 000000000..8def0a203 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_frsqrtex.s @@ -0,0 +1,27 @@ +test_frsqrtex_1: + #_ REGISTER_IN f1 4.0 + frsqrte. f3, f1 + blr + #_ REGISTER_OUT f3 0.48535156250000000 + #_ REGISTER_OUT f1 4.0 + +test_frsqrtex_2: + #_ REGISTER_IN f1 16.0 + frsqrte. f3, f1 + blr + #_ REGISTER_OUT f3 0.24267578125000000 + #_ REGISTER_OUT f1 16.0 + +test_frsqrtex_3: + #_ REGISTER_IN f1 1.0 + frsqrte. f3, f1 + blr + #_ REGISTER_OUT f3 0.97070312500000000 + #_ REGISTER_OUT f1 1.0 + +test_frsqrtex_4: + #_ REGISTER_IN f1 9.0 + frsqrte. f3, f1 + blr + #_ REGISTER_OUT f3 0.32421875000000000 + #_ REGISTER_OUT f1 9.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fselx.s b/src/xenia/cpu/ppc/testing/instr_fselx.s new file mode 100644 index 000000000..eb9906091 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fselx.s @@ -0,0 +1,43 @@ +test_fselx_1: + #_ REGISTER_IN f3 [3FF0000000000000] + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fsel. f6, f3, f4, f5 + blr + #_ REGISTER_OUT f6 [4000000000000000] + #_ REGISTER_OUT f3 [3FF0000000000000] + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] + +test_fselx_2: + #_ REGISTER_IN f3 [BFF0000000000000] + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fsel. f6, f3, f4, f5 + blr + #_ REGISTER_OUT f6 [4008000000000000] + #_ REGISTER_OUT f3 [BFF0000000000000] + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] + +test_fselx_3: + #_ REGISTER_IN f3 [0000000000000000] + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fsel. f6, f3, f4, f5 + blr + #_ REGISTER_OUT f6 [4000000000000000] + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] + +test_fselx_4: + #_ REGISTER_IN f3 [4010000000000000] + #_ REGISTER_IN f4 [4000000000000000] + #_ REGISTER_IN f5 [4008000000000000] + fsel. f6, f3, f4, f5 + blr + #_ REGISTER_OUT f6 [4000000000000000] + #_ REGISTER_OUT f3 [4010000000000000] + #_ REGISTER_OUT f4 [4000000000000000] + #_ REGISTER_OUT f5 [4008000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fsqrtsx.s b/src/xenia/cpu/ppc/testing/instr_fsqrtsx.s new file mode 100644 index 000000000..f111a036d --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fsqrtsx.s @@ -0,0 +1,27 @@ +test_fsqrtsx_1: + #_ REGISTER_IN f1 4.0 + fsqrts. f3, f1 + blr + #_ REGISTER_OUT f3 2.0 + #_ REGISTER_OUT f1 4.0 + +test_fsqrtsx_2: + #_ REGISTER_IN f1 16.0 + fsqrts. f3, f1 + blr + #_ REGISTER_OUT f3 4.0 + #_ REGISTER_OUT f1 16.0 + +test_fsqrtsx_3: + #_ REGISTER_IN f1 1.0 + fsqrts. f3, f1 + blr + #_ REGISTER_OUT f3 1.0 + #_ REGISTER_OUT f1 1.0 + +test_fsqrtsx_4: + #_ REGISTER_IN f1 9.0 + fsqrts. f3, f1 + blr + #_ REGISTER_OUT f3 3.0 + #_ REGISTER_OUT f1 9.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fsqrtx.s b/src/xenia/cpu/ppc/testing/instr_fsqrtx.s new file mode 100644 index 000000000..dafe4c8c6 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fsqrtx.s @@ -0,0 +1,27 @@ +test_fsqrtx_1: + #_ REGISTER_IN f1 4.0 + fsqrt. f3, f1 + blr + #_ REGISTER_OUT f3 2.0 + #_ REGISTER_OUT f1 4.0 + +test_fsqrtx_2: + #_ REGISTER_IN f1 16.0 + fsqrt. f3, f1 + blr + #_ REGISTER_OUT f3 4.0 + #_ REGISTER_OUT f1 16.0 + +test_fsqrtx_3: + #_ REGISTER_IN f1 1.0 + fsqrt. f3, f1 + blr + #_ REGISTER_OUT f3 1.0 + #_ REGISTER_OUT f1 1.0 + +test_fsqrtx_4: + #_ REGISTER_IN f1 9.0 + fsqrt. f3, f1 + blr + #_ REGISTER_OUT f3 3.0 + #_ REGISTER_OUT f1 9.0 diff --git a/src/xenia/cpu/ppc/testing/instr_fsubsx.s b/src/xenia/cpu/ppc/testing/instr_fsubsx.s new file mode 100644 index 000000000..961d33e11 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fsubsx.s @@ -0,0 +1,35 @@ +test_fsubsx_1: + #_ REGISTER_IN f4 [4008000000000000] + #_ REGISTER_IN f5 [3FF0000000000000] + fsubs. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4000000000000000] + #_ REGISTER_OUT f4 [4008000000000000] + #_ REGISTER_OUT f5 [3FF0000000000000] + +test_fsubsx_2: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [3FF0000000000000] + fsubs. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [3FF0000000000000] + +test_fsubsx_3: + #_ REGISTER_IN f4 [4010000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fsubs. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4008000000000000] + #_ REGISTER_OUT f4 [4010000000000000] + #_ REGISTER_OUT f5 [4000000000000000] + +test_fsubsx_4: + #_ REGISTER_IN f4 [0000000000000000] + #_ REGISTER_IN f5 [0000000000000000] + fsubs. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + #_ REGISTER_OUT f5 [0000000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_fsubx.s b/src/xenia/cpu/ppc/testing/instr_fsubx.s new file mode 100644 index 000000000..48b4a744e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_fsubx.s @@ -0,0 +1,35 @@ +test_fsubx_1: + #_ REGISTER_IN f4 [4008000000000000] + #_ REGISTER_IN f5 [3FF0000000000000] + fsub. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4000000000000000] + #_ REGISTER_OUT f4 [4008000000000000] + #_ REGISTER_OUT f5 [3FF0000000000000] + +test_fsubx_2: + #_ REGISTER_IN f4 [3FF0000000000000] + #_ REGISTER_IN f5 [3FF0000000000000] + fsub. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [3FF0000000000000] + #_ REGISTER_OUT f5 [3FF0000000000000] + +test_fsubx_3: + #_ REGISTER_IN f4 [4010000000000000] + #_ REGISTER_IN f5 [4000000000000000] + fsub. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [4008000000000000] + #_ REGISTER_OUT f4 [4010000000000000] + #_ REGISTER_OUT f5 [4000000000000000] + +test_fsubx_4: + #_ REGISTER_IN f4 [0000000000000000] + #_ REGISTER_IN f5 [0000000000000000] + fsub. f3, f4, f5 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f4 [0000000000000000] + #_ REGISTER_OUT f5 [0000000000000000] diff --git a/src/xenia/cpu/ppc/testing/instr_icbi.s b/src/xenia/cpu/ppc/testing/instr_icbi.s new file mode 100644 index 000000000..de6bd27d6 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_icbi.s @@ -0,0 +1,31 @@ +test_icbi_1: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 0 + icbi r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 0 + +test_icbi_2: + #_ REGISTER_IN r4 0x00001000 + #_ REGISTER_IN r5 64 + icbi r4, r5 + blr + #_ REGISTER_OUT r4 0x00001000 + #_ REGISTER_OUT r5 64 + +test_icbi_3: + #_ REGISTER_IN r4 0 + #_ REGISTER_IN r5 0x00001000 + icbi r4, r5 + blr + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 0x00001000 + +test_icbi_4: + #_ REGISTER_IN r4 0x00002000 + #_ REGISTER_IN r5 128 + icbi r4, r5 + blr + #_ REGISTER_OUT r4 0x00002000 + #_ REGISTER_OUT r5 128 diff --git a/src/xenia/cpu/ppc/testing/instr_isync.s b/src/xenia/cpu/ppc/testing/instr_isync.s new file mode 100644 index 000000000..523c8b9ae --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_isync.s @@ -0,0 +1,13 @@ +test_isync_1: + #_ REGISTER_IN r3 0x0000000000000001 + isync + blr + #_ REGISTER_OUT r3 0x0000000000000001 + +test_isync_2: + #_ REGISTER_IN r4 0x0000000012345678 + #_ REGISTER_IN r5 0xABCDEF0123456789 + isync + blr + #_ REGISTER_OUT r4 0x0000000012345678 + #_ REGISTER_OUT r5 0xABCDEF0123456789 diff --git a/src/xenia/cpu/ppc/testing/instr_lbz.s b/src/xenia/cpu/ppc/testing/instr_lbz.s new file mode 100644 index 000000000..45be26e61 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lbz.s @@ -0,0 +1,50 @@ +test_lbz_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A] + #_ REGISTER_IN r4 0x0000000010001000 + lbz r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lbz_offset: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88] + #_ REGISTER_IN r4 0x0000000010001000 + lbz r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000033 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lbzu_1: + #_ MEMORY_IN 0x0000000010001000 [AA, BB, CC, DD, EE, FF, 00, 11] + #_ REGISTER_IN r4 0x0000000010001000 + lbzu r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x00000000000000CC + #_ REGISTER_OUT r4 0x0000000010001004 + +test_lbzx_1: + #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000003 + lbzx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000003 + +test_lbzux_1: + #_ MEMORY_IN 0x0000000010001000 [FF, EE, DD, CC, BB, AA, 99, 88] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000005 + lbzux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001005 + +test_lbz_max: + #_ MEMORY_IN 0x0000000010001000 [FF, 00, 7F, 80, 01, FE, 02, FD] + #_ REGISTER_IN r4 0x0000000010001000 + lbz r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 diff --git a/src/xenia/cpu/ppc/testing/instr_lbzu.s b/src/xenia/cpu/ppc/testing/instr_lbzu.s new file mode 100644 index 000000000..7f0d65242 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lbzu.s @@ -0,0 +1,35 @@ +test_lbzu_1: + #_ MEMORY_IN 0x0000000010001000 [AB, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lbzu r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lbzu_2: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, CD, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lbzu r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001004 + +test_lbzux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, EF, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000006 + lbzux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001006 + #_ REGISTER_OUT r5 0x0000000000000006 + +test_lbzux_2: + #_ MEMORY_IN 0x0000000010001000 [12, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + lbzux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_ld.s b/src/xenia/cpu/ppc/testing/instr_ld.s new file mode 100644 index 000000000..678d137e1 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_ld.s @@ -0,0 +1,43 @@ +test_ld_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A, BC, DE, F0, 11] + #_ REGISTER_IN r4 0x0000000010001000 + ld r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x000BCD00EF001200 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_ld_offset: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF, 00] + #_ REGISTER_IN r4 0x0000000010001000 + ld r3, 8(r4) + blr + #_ REGISTER_OUT r3 0x5500660077008800 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_ldu_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, AA, BB, CC, DD, EE, FF, 00, 11] + #_ REGISTER_IN r4 0x0000000010001000 + ldu r3, 8(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001008 + +test_ldx_1: + #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0, FE, DC, BA, 98, 76, 54, 32, 10] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + ldx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x9A00BC00DE00F000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000008 + +test_ldux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, FF, EE, DD, CC, BB, AA, 99, 88] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000010 + ldux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001010 + #_ REGISTER_OUT r5 0x0000000000000010 diff --git a/src/xenia/cpu/ppc/testing/instr_ldu.s b/src/xenia/cpu/ppc/testing/instr_ldu.s new file mode 100644 index 000000000..83a98f909 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_ldu.s @@ -0,0 +1,35 @@ +test_ldu_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 90] + #_ REGISTER_IN r4 0x0000000010001000 + ldu r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x000BCD00EF001200 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_ldu_2: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 12, 34, 56, 78, 9A, BC, DE, F0] + #_ REGISTER_IN r4 0x0000000010001000 + ldu r3, 8(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001008 + +test_ldux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, FE, DC, BA, 98, 76, 54, 32, 10] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + ldux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001008 + #_ REGISTER_OUT r5 0x0000000000000008 + +test_ldux_2: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + ldux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0001220033004400 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_lfd.s b/src/xenia/cpu/ppc/testing/instr_lfd.s new file mode 100644 index 000000000..7c07f2691 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lfd.s @@ -0,0 +1,43 @@ +test_lfd_1: + #_ MEMORY_IN 0x0000000010001000 [3F, F0, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lfd f3, 0(r4) + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT f3 0x000FF00000000000 + +test_lfd_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 40, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lfd f3, 8(r4) + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT f3 0x0000000000000000 + +test_lfdu_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 40, 08, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lfdu f3, 8(r4) + blr + #_ REGISTER_OUT r4 0x0000000010001008 + #_ REGISTER_OUT f3 0x0000000000000000 + +test_lfdx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 40, 10, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + lfdx f3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000008 + #_ REGISTER_OUT f3 0x0000000000000000 + +test_lfdux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 40, 14, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + lfdux f3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001008 + #_ REGISTER_OUT r5 0x0000000000000008 + #_ REGISTER_OUT f3 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_lfs.s b/src/xenia/cpu/ppc/testing/instr_lfs.s new file mode 100644 index 000000000..6534a6f87 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lfs.s @@ -0,0 +1,43 @@ +test_lfs_1: + #_ MEMORY_IN 0x0000000010001000 [3F, 80, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lfs f3, 0(r4) + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT f3 0x37DF000000000000 + +test_lfs_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 40, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lfs f3, 4(r4) + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT f3 0x0000000000000000 + +test_lfsu_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 40, 40, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lfsu f3, 4(r4) + blr + #_ REGISTER_OUT r4 0x0000000010001004 + #_ REGISTER_OUT f3 0x0000000000000000 + +test_lfsx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 40, 80, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + lfsx f3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + #_ REGISTER_OUT f3 0x0000000000000000 + +test_lfsux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 40, A0, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + lfsux f3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001004 + #_ REGISTER_OUT r5 0x0000000000000004 + #_ REGISTER_OUT f3 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_lha.s b/src/xenia/cpu/ppc/testing/instr_lha.s new file mode 100644 index 000000000..4e5baface --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lha.s @@ -0,0 +1,43 @@ +test_lha_positive: + #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 7F, FF, 00, 01] + #_ REGISTER_IN r4 0x0000000010001000 + lha r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000002 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lha_negative: + #_ MEMORY_IN 0x0000000010001000 [FF, FF, 80, 00, 80, 01, AA, BB] + #_ REGISTER_IN r4 0x0000000010001000 + lha r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x000000000000000F + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lhau_positive: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88] + #_ REGISTER_IN r4 0x0000000010001000 + lhau r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000000003300 + #_ REGISTER_OUT r4 0x0000000010001004 + +test_lhax_negative: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 80, 00, FF, FF] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + lhax r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_lhaux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, AA, BB] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000006 + lhaux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001006 + #_ REGISTER_OUT r5 0x0000000000000006 diff --git a/src/xenia/cpu/ppc/testing/instr_lhau.s b/src/xenia/cpu/ppc/testing/instr_lhau.s new file mode 100644 index 000000000..131f2485e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lhau.s @@ -0,0 +1,35 @@ +test_lhau_1: + #_ MEMORY_IN 0x0000000010001000 [7F, FF, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lhau r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x000000000000000F + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lhau_2: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 80, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lhau r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001004 + +test_lhaux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 12, 34] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000006 + lhaux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001006 + #_ REGISTER_OUT r5 0x0000000000000006 + +test_lhaux_2: + #_ MEMORY_IN 0x0000000010001000 [FF, FF, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + lhaux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000000000000000F + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_lhbrx.s b/src/xenia/cpu/ppc/testing/instr_lhbrx.s new file mode 100644 index 000000000..ffaf0a326 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lhbrx.s @@ -0,0 +1,29 @@ +test_lhbrx_1: + #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0 + lhbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000200 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0 + +test_lhbrx_2: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 01] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 2 + lhbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000000000CD + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 2 + +test_lhbrx_3: + #_ MEMORY_IN 0x0000000010001000 [FF, FE, FD, FC] + #_ REGISTER_IN r4 0 + #_ REGISTER_IN r5 0x0000000010001000 + lhbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000F00 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 0x0000000010001000 diff --git a/src/xenia/cpu/ppc/testing/instr_lhz.s b/src/xenia/cpu/ppc/testing/instr_lhz.s new file mode 100644 index 000000000..970fa5af4 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lhz.s @@ -0,0 +1,43 @@ +test_lhz_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A] + #_ REGISTER_IN r4 0x0000000010001000 + lhz r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x000000000000000B + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lhz_offset: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88] + #_ REGISTER_IN r4 0x0000000010001000 + lhz r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000000003300 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lhzu_1: + #_ MEMORY_IN 0x0000000010001000 [AA, BB, CC, DD, EE, FF, 00, 11] + #_ REGISTER_IN r4 0x0000000010001000 + lhzu r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x000000000000CC00 + #_ REGISTER_OUT r4 0x0000000010001004 + +test_lhzx_1: + #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000002 + lhzx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000003400 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000002 + +test_lhzux_1: + #_ MEMORY_IN 0x0000000010001000 [FF, EE, DD, CC, BB, AA, 99, 88] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000006 + lhzux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000000000000CC00 + #_ REGISTER_OUT r4 0x0000000010001006 + #_ REGISTER_OUT r5 0x0000000000000006 diff --git a/src/xenia/cpu/ppc/testing/instr_lhzu.s b/src/xenia/cpu/ppc/testing/instr_lhzu.s new file mode 100644 index 000000000..a16c0130e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lhzu.s @@ -0,0 +1,35 @@ +test_lhzu_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lhzu r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x000000000000000B + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lhzu_2: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 12, 34, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lhzu r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001004 + +test_lhzux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 56, 78] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000006 + lhzux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001006 + #_ REGISTER_OUT r5 0x0000000000000006 + +test_lhzux_2: + #_ MEMORY_IN 0x0000000010001000 [9A, BC, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + lhzux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000000000000000A + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_lmw.s b/src/xenia/cpu/ppc/testing/instr_lmw.s new file mode 100644 index 000000000..ad2b09488 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lmw.s @@ -0,0 +1,23 @@ +test_lmw_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 01, 00, 00, 00, 02, 00, 00, 00, 03] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r30 0 + #_ REGISTER_IN r31 0 + lmw r30, 0(r4) + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r30 0x0000000000000000 + #_ REGISTER_OUT r31 0x0000000000000100 + +test_lmw_2: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 0A, 00, 00, 00, 0B, 00, 00, 00, 0C, 00, 00, 00, 0D] + #_ REGISTER_IN r4 0x0000000010000FF8 + #_ REGISTER_IN r29 0 + #_ REGISTER_IN r30 0 + #_ REGISTER_IN r31 0 + lmw r29, 8(r4) + blr + #_ REGISTER_OUT r4 0x0000000010000FF8 + #_ REGISTER_OUT r29 0x0000000000000000 + #_ REGISTER_OUT r30 0x0000000000000A00 + #_ REGISTER_OUT r31 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_lvlx128.s b/src/xenia/cpu/ppc/testing/instr_lvlx128.s new file mode 100644 index 000000000..68e2b1af9 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lvlx128.s @@ -0,0 +1,18 @@ +test_lvlx128_1: + # Load vector left - loads from EA to high bytes + # EA=0x10001077, aligns to 0x10001070, offset=7 + #_ MEMORY_IN 0x0000000010001070 [00, 00, 00, 00, 00, 00, 00, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12] + #_ REGISTER_IN r4 0x0000000010001077 + lvlx128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001077 + #_ REGISTER_OUT v3 [00000000, 0000000A, 00000000, 00000000] + +test_lvlx128_2: + # Test aligned address + #_ MEMORY_IN 0x0000000010001000 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, FA, FB, FC, FD, FE, FF] + #_ REGISTER_IN r4 0x0000000010001000 + lvlx128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT v3 [0000F100, F200F300, F400F500, F600F700] diff --git a/src/xenia/cpu/ppc/testing/instr_lvlxl128.s b/src/xenia/cpu/ppc/testing/instr_lvlxl128.s new file mode 100644 index 000000000..666d1653b --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lvlxl128.s @@ -0,0 +1,9 @@ +test_lvlxl128_1: + # Load vector left with cache hint + # EA=0x10001077, aligns to 0x10001070, offset=7 + #_ MEMORY_IN 0x0000000010001070 [00, 00, 00, 00, 00, 00, 00, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12] + #_ REGISTER_IN r4 0x0000000010001077 + lvlxl128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001077 + #_ REGISTER_OUT v3 [00000000, 0000000A, 00000000, 00000000] diff --git a/src/xenia/cpu/ppc/testing/instr_lvrx128.s b/src/xenia/cpu/ppc/testing/instr_lvrx128.s new file mode 100644 index 000000000..81a881a0f --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lvrx128.s @@ -0,0 +1,18 @@ +test_lvrx128_1: + # Load vector right - loads from EA to low bytes + # EA=0x10001077, aligns to 0x10001070, offset=7 + #_ MEMORY_IN 0x0000000010001070 [00, 00, 00, 00, 00, 00, 00, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12] + #_ REGISTER_IN r4 0x0000000010001077 + lvrx128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001077 + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + +test_lvrx128_2: + # Test aligned address + #_ MEMORY_IN 0x0000000010001000 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, FA, FB, FC, FD, FE, FF] + #_ REGISTER_IN r4 0x0000000010001000 + lvrx128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] diff --git a/src/xenia/cpu/ppc/testing/instr_lvrxl128.s b/src/xenia/cpu/ppc/testing/instr_lvrxl128.s new file mode 100644 index 000000000..062b07cff --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lvrxl128.s @@ -0,0 +1,9 @@ +test_lvrxl128_1: + # Load vector right with cache hint + # EA=0x10001077, aligns to 0x10001070, offset=7 + #_ MEMORY_IN 0x0000000010001070 [00, 00, 00, 00, 00, 00, 00, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12] + #_ REGISTER_IN r4 0x0000000010001077 + lvrxl128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001077 + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] diff --git a/src/xenia/cpu/ppc/testing/instr_lvsl128.s b/src/xenia/cpu/ppc/testing/instr_lvsl128.s new file mode 100644 index 000000000..1db4d3027 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lvsl128.s @@ -0,0 +1,20 @@ +test_lvsl128_1: + #_ REGISTER_IN r4 0x1070 + lvsl128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x1070 + #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] + +test_lvsl128_2: + #_ REGISTER_IN r4 0x1071 + lvsl128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x1071 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + +test_lvsl128_3: + #_ REGISTER_IN r4 0x107F + lvsl128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x107F + #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E] diff --git a/src/xenia/cpu/ppc/testing/instr_lvsr128.s b/src/xenia/cpu/ppc/testing/instr_lvsr128.s new file mode 100644 index 000000000..a381c320c --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lvsr128.s @@ -0,0 +1,20 @@ +test_lvsr128_1: + #_ REGISTER_IN r4 0x1070 + lvsr128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x1070 + #_ REGISTER_OUT v3 [10111213, 14151617, 18191A1B, 1C1D1E1F] + +test_lvsr128_2: + #_ REGISTER_IN r4 0x1071 + lvsr128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x1071 + #_ REGISTER_OUT v3 [0F101112, 13141516, 1718191A, 1B1C1D1E] + +test_lvsr128_3: + #_ REGISTER_IN r4 0x107F + lvsr128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x107F + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] diff --git a/src/xenia/cpu/ppc/testing/instr_lvxl128.s b/src/xenia/cpu/ppc/testing/instr_lvxl128.s new file mode 100644 index 000000000..4f2ce4293 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lvxl128.s @@ -0,0 +1,22 @@ +test_lvxl128_1: + # Basic 128-bit aligned load with cache hint + #_ MEMORY_IN 0x0000000010001000 [01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10] + #_ REGISTER_IN r4 0x0000000010001000 + li r5, 0 + lvxl128 v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT v3 [00010200, 03000400, 05000600, 07000800] + +test_lvxl128_2: + # Test with offset + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ MEMORY_IN 0x0000000010001010 [AA, BB, CC, DD, EE, FF, 00, 11, 22, 33, 44, 55, 66, 77, 88, 99] + #_ REGISTER_IN r4 0x0000000010001000 + li r5, 16 + lvxl128 v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 16 + #_ REGISTER_OUT v3 [000ABB00, CC00DD00, EE00FF00, 00001100] diff --git a/src/xenia/cpu/ppc/testing/instr_lwa.s b/src/xenia/cpu/ppc/testing/instr_lwa.s new file mode 100644 index 000000000..0ca05b8e9 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lwa.s @@ -0,0 +1,45 @@ +test_lwa_positive: + #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 7F, FF, FF, FF] + #_ REGISTER_IN r4 0x0000000010001000 + lwa r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x0000000000023400 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lwa_negative: + #_ MEMORY_IN 0x0000000010001000 [FF, FF, FF, FF, 80, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lwa r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x00000000000FFF00 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lwax_positive: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 01, 11, 22, 33, 44] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + lwax r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_lwax_negative: + #_ MEMORY_IN 0x0000000010001000 [80, 00, 00, 01, AA, BB, CC, DD] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + lwax r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + +test_lwaux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, FE, DC, BA, 98] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + lwaux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001008 + #_ REGISTER_OUT r5 0x0000000000000008 diff --git a/src/xenia/cpu/ppc/testing/instr_lwbrx.s b/src/xenia/cpu/ppc/testing/instr_lwbrx.s new file mode 100644 index 000000000..941fb05a3 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lwbrx.s @@ -0,0 +1,29 @@ +test_lwbrx_1: + #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0 + lwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000340200 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0 + +test_lwbrx_2: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 01, 23, 45, 67, 89] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 4 + lwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000000100EF + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 4 + +test_lwbrx_3: + #_ MEMORY_IN 0x0000000010001000 [FF, FE, FD, FC, FB, FA, F9, F8] + #_ REGISTER_IN r4 0 + #_ REGISTER_IN r5 0x0000000010001000 + lwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000FE0F00 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 0x0000000010001000 diff --git a/src/xenia/cpu/ppc/testing/instr_lwz.s b/src/xenia/cpu/ppc/testing/instr_lwz.s new file mode 100644 index 000000000..4e199a155 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lwz.s @@ -0,0 +1,43 @@ +test_lwz_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A] + #_ REGISTER_IN r4 0x0000000010001000 + lwz r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x00000000000BCD00 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lwz_offset: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88] + #_ REGISTER_IN r4 0x0000000010001000 + lwz r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000033004400 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lwzu_1: + #_ MEMORY_IN 0x0000000010001000 [AA, BB, CC, DD, EE, FF, 00, 11] + #_ REGISTER_IN r4 0x0000000010001000 + lwzu r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x00000000CC00DD00 + #_ REGISTER_OUT r4 0x0000000010001004 + +test_lwzx_1: + #_ MEMORY_IN 0x0000000010001000 [12, 34, 56, 78, 9A, BC, DE, F0] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + lwzx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000056007800 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_lwzux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, FF, EE, DD, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + lwzux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001008 + #_ REGISTER_OUT r5 0x0000000000000008 diff --git a/src/xenia/cpu/ppc/testing/instr_lwzu.s b/src/xenia/cpu/ppc/testing/instr_lwzu.s new file mode 100644 index 000000000..c328ec569 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lwzu.s @@ -0,0 +1,35 @@ +test_lwzu_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + lwzu r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x00000000000BCD00 + #_ REGISTER_OUT r4 0x0000000010001000 + +test_lwzu_2: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 12, 34, 56, 78] + #_ REGISTER_IN r4 0x0000000010001000 + lwzu r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001004 + +test_lwzux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 9A, BC, DE, F0] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000006 + lwzux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000010001006 + #_ REGISTER_OUT r5 0x0000000000000006 + +test_lwzux_2: + #_ MEMORY_IN 0x0000000010001000 [FE, DC, BA, 98, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + lwzux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000000EDC00 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_lxarx.s b/src/xenia/cpu/ppc/testing/instr_lxarx.s new file mode 100644 index 000000000..3bc05314f --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lxarx.s @@ -0,0 +1,39 @@ +test_lwarx_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + lwarx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000000BCD00 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + +test_lwarx_offset: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + lwarx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000033004400 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_ldarx_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + ldarx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000BCD00EF001200 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + +test_ldarx_offset: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + ldarx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x3300440055006600 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 diff --git a/src/xenia/cpu/ppc/testing/instr_lxbrx.s b/src/xenia/cpu/ppc/testing/instr_lxbrx.s new file mode 100644 index 000000000..eb8f3cc48 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_lxbrx.s @@ -0,0 +1,59 @@ +test_lhbrx_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + lhbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000B00 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + +test_lhbrx_offset: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + lhbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000033 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_lwbrx_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + lwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000CD0B00 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + +test_lwbrx_offset: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + lwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000440033 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_ldbrx_1: + #_ MEMORY_IN 0x0000000010001000 [AB, CD, EF, 12, 34, 56, 78, 9A] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + ldbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x001200EF00CD0B00 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + +test_ldbrx_offset: + #_ MEMORY_IN 0x0000000010001000 [11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + ldbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0066005500440033 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 diff --git a/src/xenia/cpu/ppc/testing/instr_mcrfs.s b/src/xenia/cpu/ppc/testing/instr_mcrfs.s new file mode 100644 index 000000000..3c84876cb --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mcrfs.s @@ -0,0 +1,19 @@ +test_mcrfs_1: + #_ REGISTER_IN f1 1.0 + #_ REGISTER_IN f2 2.0 + fadds f3, f1, f2 + mcrfs 1, 0 + blr + #_ REGISTER_OUT f1 1.0 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 3.0 + +test_mcrfs_2: + #_ REGISTER_IN f1 0x7FF0000000000001 + #_ REGISTER_IN f2 1.0 + fadd f3, f1, f2 + mcrfs 2, 0 + blr + #_ REGISTER_OUT f1 0x7FF0000000000001 + #_ REGISTER_OUT f2 1.0 + #_ REGISTER_OUT f3 0x7FF8000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_mcrxr.s b/src/xenia/cpu/ppc/testing/instr_mcrxr.s new file mode 100644 index 000000000..6ee2f99c1 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mcrxr.s @@ -0,0 +1,19 @@ +test_mcrxr_1: + #_ REGISTER_IN r3 0x0000000000000001 + #_ REGISTER_IN r4 0x0000000000000001 + addc r5, r3, r4 + mcrxr 1 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000002 + +test_mcrxr_2: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x0000000000000001 + addc r5, r3, r4 + mcrxr 2 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_mffsx.s b/src/xenia/cpu/ppc/testing/instr_mffsx.s new file mode 100644 index 000000000..da5268eba --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mffsx.s @@ -0,0 +1,31 @@ +test_mffsx_1: + #_ REGISTER_IN f1 [0000000000000000] + mtfsf 0xFF, f1 + mffs. f3 + blr + #_ REGISTER_OUT f3 [0000000000000000] + #_ REGISTER_OUT f1 [0000000000000000] + +test_mffsx_2: + #_ REGISTER_IN f1 [0000000000000005] + mtfsf 0xFF, f1 + mffs. f4 + blr + #_ REGISTER_OUT f4 [0000000000000005] + #_ REGISTER_OUT f1 [0000000000000005] + +test_mffsx_3: + #_ REGISTER_IN f1 [00000000000000F0] + mtfsf 0xFF, f1 + mffs. f5 + blr + #_ REGISTER_OUT f5 [00000000000000F0] + #_ REGISTER_OUT f1 [00000000000000F0] + +test_mffsx_4: + #_ REGISTER_IN f1 [0000000012345678] + mtfsf 0xFF, f1 + mffs. f6 + blr + #_ REGISTER_OUT f6 [0000000012345678] + #_ REGISTER_OUT f1 [0000000012345678] diff --git a/src/xenia/cpu/ppc/testing/instr_mfmsr.s b/src/xenia/cpu/ppc/testing/instr_mfmsr.s new file mode 100644 index 000000000..5f8d6087d --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mfmsr.s @@ -0,0 +1,11 @@ +test_mfmsr_1: + #_ REGISTER_IN r3 0x0000000000000000 + mfmsr r3 + blr + #_ REGISTER_OUT r3 0x0000000000009030 + +test_mfmsr_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + mfmsr r4 + blr + #_ REGISTER_OUT r4 0x0000000000009030 diff --git a/src/xenia/cpu/ppc/testing/instr_mfspr.s b/src/xenia/cpu/ppc/testing/instr_mfspr.s new file mode 100644 index 000000000..f41f3ae0c --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mfspr.s @@ -0,0 +1,28 @@ +test_mfspr_xer: + #_ REGISTER_IN r3 0x0000000000000001 + #_ REGISTER_IN r4 0x0000000000000001 + addc r5, r3, r4 + mfspr r6, xer + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000002 + #_ REGISTER_OUT r6 0x0000000000000000 + +test_mfspr_lr: + #_ REGISTER_IN r3 0x0000000012345678 + mflr r5 + mtlr r3 + mfspr r4, lr + mtlr r5 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000012345678 + +test_mfspr_ctr: + #_ REGISTER_IN r3 0x00000000ABCDEF01 + mtctr r3 + mfspr r4, ctr + blr + #_ REGISTER_OUT r3 0x00000000ABCDEF01 + #_ REGISTER_OUT r4 0x00000000ABCDEF01 diff --git a/src/xenia/cpu/ppc/testing/instr_mftb.s b/src/xenia/cpu/ppc/testing/instr_mftb.s new file mode 100644 index 000000000..e5a1c6da5 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mftb.s @@ -0,0 +1,26 @@ +test_mftb_1: + #_ REGISTER_IN r3 0x0000000000000000 + #_ REGISTER_IN r4 0x0000000000000000 + #_ REGISTER_IN r5 0x0000000000000000 + mftb r3, 268 + mftb r4, 268 + cmpd r4, r3 + li r5, 0 + bgt .+8 + b .+8 + li r5, 1 + blr + #_ REGISTER_OUT r5 0x0000000000000001 + +test_mftb_2: + #_ REGISTER_IN r3 0x0000000000000000 + #_ REGISTER_IN r4 0x0000000000000000 + #_ REGISTER_IN r5 0x0000000000000000 + mftb r3, 269 + mftb r4, 269 + cmpd r4, r3 + li r5, 0 + blt .+8 + li r5, 1 + blr + #_ REGISTER_OUT r5 0x0000000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_mfvscr.s b/src/xenia/cpu/ppc/testing/instr_mfvscr.s new file mode 100644 index 000000000..4ddefb9ec --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mfvscr.s @@ -0,0 +1,11 @@ +test_mfvscr_1: + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] + mfvscr v3 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00010000] + +test_mtvscr_1: + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00010001] + mtvscr v3 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00010001] diff --git a/src/xenia/cpu/ppc/testing/instr_mtcrf.s b/src/xenia/cpu/ppc/testing/instr_mtcrf.s new file mode 100644 index 000000000..5a4686cd3 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mtcrf.s @@ -0,0 +1,23 @@ +test_mtcrf_1: + #_ REGISTER_IN r3 0x0000000012345678 + mtcrf 0xFF, r3 + mfcr r4 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000012345678 + +test_mtcrf_2: + #_ REGISTER_IN r3 0x00000000ABCDEF01 + mtcrf 0x0F, r3 + mfcr r4 + blr + #_ REGISTER_OUT r3 0x00000000ABCDEF01 + #_ REGISTER_OUT r4 0x000000000000EF01 + +test_mtcrf_3: + #_ REGISTER_IN r3 0x00000000F0F0F0F0 + mtcrf 0xAA, r3 + mfcr r4 + blr + #_ REGISTER_OUT r3 0x00000000F0F0F0F0 + #_ REGISTER_OUT r4 0x00000000F0F0F0F0 diff --git a/src/xenia/cpu/ppc/testing/instr_mtfsfix.s b/src/xenia/cpu/ppc/testing/instr_mtfsfix.s new file mode 100644 index 000000000..761b4d688 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mtfsfix.s @@ -0,0 +1,15 @@ +test_mtfsfix_1: + mtfsfi. 0, 0 + blr + +test_mtfsfix_2: + mtfsfi. 1, 1 + blr + +test_mtfsfix_3: + mtfsfi. 7, 15 + blr + +test_mtfsfix_4: + mtfsfi. 0, 7 + blr diff --git a/src/xenia/cpu/ppc/testing/instr_mtfsfx.s b/src/xenia/cpu/ppc/testing/instr_mtfsfx.s new file mode 100644 index 000000000..bad0f12d5 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mtfsfx.s @@ -0,0 +1,23 @@ +test_mtfsfx_1: + #_ REGISTER_IN f1 [0000000000000001] + mtfsf. 0xFF, f1 + blr + #_ REGISTER_OUT f1 [0000000000000001] + +test_mtfsfx_2: + #_ REGISTER_IN f1 [0000000000000000] + mtfsf. 0xFF, f1 + blr + #_ REGISTER_OUT f1 [0000000000000000] + +test_mtfsfx_3: + #_ REGISTER_IN f1 [0000000000000007] + mtfsf. 0xFF, f1 + blr + #_ REGISTER_OUT f1 [0000000000000007] + +test_mtfsfx_4: + #_ REGISTER_IN f1 [00000000000000FF] + mtfsf. 0xFF, f1 + blr + #_ REGISTER_OUT f1 [00000000000000FF] diff --git a/src/xenia/cpu/ppc/testing/instr_mtmsr.s b/src/xenia/cpu/ppc/testing/instr_mtmsr.s new file mode 100644 index 000000000..b2fb5ed9c --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mtmsr.s @@ -0,0 +1,11 @@ +test_mtmsr_1: + #_ REGISTER_IN r3 0x0000000000000000 + mtmsr r3 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + +test_mtmsr_2: + #_ REGISTER_IN r4 0x0000000000001234 + mtmsr r4 + blr + #_ REGISTER_OUT r4 0x0000000000001234 diff --git a/src/xenia/cpu/ppc/testing/instr_mtmsrd.s b/src/xenia/cpu/ppc/testing/instr_mtmsrd.s new file mode 100644 index 000000000..804777d04 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mtmsrd.s @@ -0,0 +1,11 @@ +test_mtmsrd_1: + #_ REGISTER_IN r3 0x0000000000000000 + mtmsrd r3 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + +test_mtmsrd_2: + #_ REGISTER_IN r4 0x0000000000001234 + mtmsrd r4 + blr + #_ REGISTER_OUT r4 0x0000000000001234 diff --git a/src/xenia/cpu/ppc/testing/instr_mtspr.s b/src/xenia/cpu/ppc/testing/instr_mtspr.s new file mode 100644 index 000000000..107a3250f --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mtspr.s @@ -0,0 +1,25 @@ +test_mtspr_xer: + #_ REGISTER_IN r3 0x0000000020000000 + mtspr xer, r3 + mfspr r4, xer + blr + #_ REGISTER_OUT r3 0x0000000020000000 + #_ REGISTER_OUT r4 0x0000000020000000 + +test_mtspr_lr: + #_ REGISTER_IN r3 0x0000000012345678 + mflr r5 + mtspr lr, r3 + mflr r4 + mtlr r5 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000012345678 + +test_mtspr_ctr: + #_ REGISTER_IN r3 0x00000000ABCDEF01 + mtspr ctr, r3 + mfctr r4 + blr + #_ REGISTER_OUT r3 0x00000000ABCDEF01 + #_ REGISTER_OUT r4 0x00000000ABCDEF01 diff --git a/src/xenia/cpu/ppc/testing/instr_mulhdux.s b/src/xenia/cpu/ppc/testing/instr_mulhdux.s new file mode 100644 index 000000000..4af05dcdd --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mulhdux.s @@ -0,0 +1,35 @@ +test_mulhdux_1: + #_ REGISTER_IN r4 0x0000000100000000 + #_ REGISTER_IN r5 0x0000000100000000 + mulhdu. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000100000000 + #_ REGISTER_OUT r5 0x0000000100000000 + +test_mulhdux_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000002 + mulhdu. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000002 + +test_mulhdux_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + mulhdu. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + +test_mulhdux_4: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000001 + mulhdu. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_mulhdx.s b/src/xenia/cpu/ppc/testing/instr_mulhdx.s new file mode 100644 index 000000000..38dde11ba --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mulhdx.s @@ -0,0 +1,82 @@ +test_mulhdx_1: + #_ REGISTER_IN r4 0x0000000100000000 + #_ REGISTER_IN r5 0x0000000100000000 + mulhd. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_mulhdx_1_constant: + lis r4, 0x0001 + sldi r4, r4, 32 + lis r5, 0x0001 + sldi r5, r5, 32 + mulhd. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000100000000 + #_ REGISTER_OUT r12 0x0000000020000000 + +test_mulhdx_negative: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000002 + mulhd. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r12 0x0000000080000000 + +test_mulhdx_max: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + mulhd. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r12 0x0000000020000000 + +test_mulhdux_1: + #_ REGISTER_IN r4 0x0000000100000000 + #_ REGISTER_IN r5 0x0000000100000000 + mulhdu. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_mulhdux_max: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + mulhdu. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r12 0x0000000080000000 + +test_mulhwx_1: + #_ REGISTER_IN r4 0x0000000000010000 + #_ REGISTER_IN r5 0x0000000000010000 + mulhw. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_mulhwux_1: + #_ REGISTER_IN r4 0x0000000000010000 + #_ REGISTER_IN r5 0x0000000000010000 + mulhwu. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_mulhwux_max: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x00000000FFFFFFFF + mulhwu. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFE + #_ REGISTER_OUT r12 0x0000000080000000 diff --git a/src/xenia/cpu/ppc/testing/instr_mulhwux.s b/src/xenia/cpu/ppc/testing/instr_mulhwux.s new file mode 100644 index 000000000..ade1e4fad --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mulhwux.s @@ -0,0 +1,35 @@ +test_mulhwux_1: + #_ REGISTER_IN r4 0x0000000000010000 + #_ REGISTER_IN r5 0x0000000000010000 + mulhwu. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000010000 + #_ REGISTER_OUT r5 0x0000000000010000 + +test_mulhwux_2: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x0000000000000002 + mulhwu. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000002 + +test_mulhwux_3: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x00000000FFFFFFFF + mulhwu. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFE + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + #_ REGISTER_OUT r5 0x00000000FFFFFFFF + +test_mulhwux_4: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000001 + mulhwu. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_mulhwx.s b/src/xenia/cpu/ppc/testing/instr_mulhwx.s new file mode 100644 index 000000000..d6cf7e4ff --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mulhwx.s @@ -0,0 +1,35 @@ +test_mulhwx_1: + #_ REGISTER_IN r4 0x0000000000010000 + #_ REGISTER_IN r5 0x0000000000010000 + mulhw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000010000 + #_ REGISTER_OUT r5 0x0000000000010000 + +test_mulhwx_2: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x0000000000000002 + mulhw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000002 + +test_mulhwx_3: + #_ REGISTER_IN r4 0x0000000080000000 + #_ REGISTER_IN r5 0x0000000000000002 + mulhw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x0000000080000000 + #_ REGISTER_OUT r5 0x0000000000000002 + +test_mulhwx_4: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000001 + mulhw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_mulldx.s b/src/xenia/cpu/ppc/testing/instr_mulldx.s new file mode 100644 index 000000000..da59a2881 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_mulldx.s @@ -0,0 +1,53 @@ +test_mulldx_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000000010 + mulld. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000010000 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_mulldx_1_constant: + li r4, 0x1000 + li r5, 0x10 + mulld. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000010000 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_mulldx_negative: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000002 + mulld. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r12 0x0000000080000000 + +test_mulldx_overflow: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + mulld. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_mullwx_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r5 0x0000000000000010 + mullw. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000010000 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_mullwx_negative: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x0000000000000002 + mullw. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r12 0x0000000080000000 diff --git a/src/xenia/cpu/ppc/testing/instr_negx.s b/src/xenia/cpu/ppc/testing/instr_negx.s new file mode 100644 index 000000000..ae803a2d2 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_negx.s @@ -0,0 +1,39 @@ +test_negx_1: + #_ REGISTER_IN r4 0x0000000000001000 + neg. r3, r4 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFF000 + #_ REGISTER_OUT r12 0x0000000080000000 + +test_negx_1_constant: + li r4, 0x1000 + neg. r3, r4 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFF000 + #_ REGISTER_OUT r12 0x0000000080000000 + +test_negx_negative: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + neg. r3, r4 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_negx_zero: + #_ REGISTER_IN r4 0x0000000000000000 + neg. r3, r4 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r12 0x0000000020000000 + +test_negx_min: + #_ REGISTER_IN r4 0x8000000000000000 + neg. r3, r4 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r12 0x0000000020000000 diff --git a/src/xenia/cpu/ppc/testing/instr_orcx.s b/src/xenia/cpu/ppc/testing/instr_orcx.s new file mode 100644 index 000000000..a65bdc686 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_orcx.s @@ -0,0 +1,35 @@ +test_orcx_1: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xAAAAAAAAAAAAAAAA + orc. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xAAAAAAAAAAAAAAAA + +test_orcx_2: + #_ REGISTER_IN r4 0xAAAAAAAAAAAAAAAA + #_ REGISTER_IN r5 0x5555555555555555 + orc. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xAAAAAAAAAAAAAAAA + #_ REGISTER_OUT r4 0xAAAAAAAAAAAAAAAA + #_ REGISTER_OUT r5 0x5555555555555555 + +test_orcx_3: + #_ REGISTER_IN r4 0x0000000000000000 + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + orc. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0000000000000000 + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + +test_orcx_4: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + #_ REGISTER_IN r5 0x0F0F0F0F0F0F0F0F + orc. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xF2F4F6F8FAFCFEF0 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + #_ REGISTER_OUT r5 0x0F0F0F0F0F0F0F0F diff --git a/src/xenia/cpu/ppc/testing/instr_rldclx.s b/src/xenia/cpu/ppc/testing/instr_rldclx.s new file mode 100644 index 000000000..bba9a49e1 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_rldclx.s @@ -0,0 +1,35 @@ +test_rldclx_1: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + #_ REGISTER_IN r5 0x0000000000000008 + rldcl. r3, r4, r5, 56 + blr + #_ REGISTER_OUT r3 0x0000000000000012 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + #_ REGISTER_OUT r5 0x0000000000000008 + +test_rldclx_2: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + #_ REGISTER_IN r5 0x0000000000000010 + rldcl. r3, r4, r5, 48 + blr + #_ REGISTER_OUT r3 0x0000000000001234 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + #_ REGISTER_OUT r5 0x0000000000000010 + +test_rldclx_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000000 + rldcl. r3, r4, r5, 32 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000000 + +test_rldclx_4: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + #_ REGISTER_IN r5 0x0000000000000020 + rldcl. r3, r4, r5, 32 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + #_ REGISTER_OUT r5 0x0000000000000020 diff --git a/src/xenia/cpu/ppc/testing/instr_rldcrx.s b/src/xenia/cpu/ppc/testing/instr_rldcrx.s new file mode 100644 index 000000000..e7bb068c3 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_rldcrx.s @@ -0,0 +1,35 @@ +test_rldcrx_1: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + #_ REGISTER_IN r5 0x0000000000000008 + rldcr. r3, r4, r5, 55 + blr + #_ REGISTER_OUT r3 0x3456789ABCDEF000 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + #_ REGISTER_OUT r5 0x0000000000000008 + +test_rldcrx_2: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + #_ REGISTER_IN r5 0x0000000000000010 + rldcr. r3, r4, r5, 47 + blr + #_ REGISTER_OUT r3 0x56789ABCDEF00000 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + #_ REGISTER_OUT r5 0x0000000000000010 + +test_rldcrx_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000000 + rldcr. r3, r4, r5, 31 + blr + #_ REGISTER_OUT r3 0xFFFFFFFF00000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000000 + +test_rldcrx_4: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + #_ REGISTER_IN r5 0x0000000000000020 + rldcr. r3, r4, r5, 31 + blr + #_ REGISTER_OUT r3 0x9ABCDEF000000000 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + #_ REGISTER_OUT r5 0x0000000000000020 diff --git a/src/xenia/cpu/ppc/testing/instr_rldiclx.s b/src/xenia/cpu/ppc/testing/instr_rldiclx.s new file mode 100644 index 000000000..2476ff3b8 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_rldiclx.s @@ -0,0 +1,27 @@ +test_rldiclx_1: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldicl. r3, r4, 8, 56 + blr + #_ REGISTER_OUT r3 0x0000000000000012 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + +test_rldiclx_2: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldicl. r3, r4, 16, 48 + blr + #_ REGISTER_OUT r3 0x0000000000001234 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + +test_rldiclx_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + rldicl. r3, r4, 0, 32 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + +test_rldiclx_4: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldicl. r3, r4, 32, 32 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 diff --git a/src/xenia/cpu/ppc/testing/instr_rldicrx.s b/src/xenia/cpu/ppc/testing/instr_rldicrx.s new file mode 100644 index 000000000..18f2afd9e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_rldicrx.s @@ -0,0 +1,27 @@ +test_rldicrx_1: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldicr. r3, r4, 8, 55 + blr + #_ REGISTER_OUT r3 0x3456789ABCDEF000 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + +test_rldicrx_2: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldicr. r3, r4, 16, 47 + blr + #_ REGISTER_OUT r3 0x56789ABCDEF00000 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + +test_rldicrx_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + rldicr. r3, r4, 0, 31 + blr + #_ REGISTER_OUT r3 0xFFFFFFFF00000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + +test_rldicrx_4: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldicr. r3, r4, 32, 31 + blr + #_ REGISTER_OUT r3 0x9ABCDEF000000000 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 diff --git a/src/xenia/cpu/ppc/testing/instr_rldicx.s b/src/xenia/cpu/ppc/testing/instr_rldicx.s new file mode 100644 index 000000000..a47420f36 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_rldicx.s @@ -0,0 +1,27 @@ +test_rldicx_1: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldic. r3, r4, 8, 48 + blr + #_ REGISTER_OUT r3 0x000000000000F000 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + +test_rldicx_2: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldic. r3, r4, 16, 40 + blr + #_ REGISTER_OUT r3 0x0000000000F00000 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + +test_rldicx_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + rldic. r3, r4, 4, 56 + blr + #_ REGISTER_OUT r3 0x00000000000000F0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + +test_rldicx_4: + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldic. r3, r4, 0, 0 + blr + #_ REGISTER_OUT r3 0x123456789ABCDEF0 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 diff --git a/src/xenia/cpu/ppc/testing/instr_rldimix.s b/src/xenia/cpu/ppc/testing/instr_rldimix.s new file mode 100644 index 000000000..eec1c2a0f --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_rldimix.s @@ -0,0 +1,31 @@ +test_rldimix_1: + #_ REGISTER_IN r3 0x0000000000000000 + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldimi. r3, r4, 8, 48 + blr + #_ REGISTER_OUT r3 0x000000000000F000 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + +test_rldimix_2: + #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldimi. r3, r4, 16, 40 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFF0FFFF + #_ REGISTER_OUT r4 0x123456789ABCDEF0 + +test_rldimix_3: + #_ REGISTER_IN r3 0x0000000000000000 + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + rldimi. r3, r4, 4, 56 + blr + #_ REGISTER_OUT r3 0x00000000000000F0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + +test_rldimix_4: + #_ REGISTER_IN r3 0xAAAAAAAAAAAAAAAA + #_ REGISTER_IN r4 0x123456789ABCDEF0 + rldimi. r3, r4, 0, 0 + blr + #_ REGISTER_OUT r3 0x123456789ABCDEF0 + #_ REGISTER_OUT r4 0x123456789ABCDEF0 diff --git a/src/xenia/cpu/ppc/testing/instr_rlwimix.s b/src/xenia/cpu/ppc/testing/instr_rlwimix.s new file mode 100644 index 000000000..a6119c049 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_rlwimix.s @@ -0,0 +1,31 @@ +test_rlwimix_1: + #_ REGISTER_IN r3 0x0000000000000000 + #_ REGISTER_IN r4 0x0000000012345678 + rlwimi. r3, r4, 8, 16, 23 + blr + #_ REGISTER_OUT r3 0x0000000000007800 + #_ REGISTER_OUT r4 0x0000000012345678 + +test_rlwimix_2: + #_ REGISTER_IN r3 0x00000000FFFFFFFF + #_ REGISTER_IN r4 0x0000000012345678 + rlwimi. r3, r4, 16, 8, 15 + blr + #_ REGISTER_OUT r3 0x00000000FF78FFFF + #_ REGISTER_OUT r4 0x0000000012345678 + +test_rlwimix_3: + #_ REGISTER_IN r3 0x0000000000000000 + #_ REGISTER_IN r4 0x00000000FFFFFFFF + rlwimi. r3, r4, 4, 20, 27 + blr + #_ REGISTER_OUT r3 0x0000000000000FF0 + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + +test_rlwimix_4: + #_ REGISTER_IN r3 0x00000000AAAAAAAA + #_ REGISTER_IN r4 0x0000000012345678 + rlwimi. r3, r4, 0, 0, 31 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000012345678 diff --git a/src/xenia/cpu/ppc/testing/instr_rlwinmx.s b/src/xenia/cpu/ppc/testing/instr_rlwinmx.s new file mode 100644 index 000000000..ac3e5f3e7 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_rlwinmx.s @@ -0,0 +1,27 @@ +test_rlwinmx_1: + #_ REGISTER_IN r4 0x0000000012345678 + rlwinm. r3, r4, 8, 16, 23 + blr + #_ REGISTER_OUT r3 0x0000000000007800 + #_ REGISTER_OUT r4 0x0000000012345678 + +test_rlwinmx_2: + #_ REGISTER_IN r4 0x0000000012345678 + rlwinm. r3, r4, 16, 8, 15 + blr + #_ REGISTER_OUT r3 0x0000000000780000 + #_ REGISTER_OUT r4 0x0000000012345678 + +test_rlwinmx_3: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + rlwinm. r3, r4, 4, 20, 27 + blr + #_ REGISTER_OUT r3 0x0000000000000FF0 + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + +test_rlwinmx_4: + #_ REGISTER_IN r4 0x0000000012345678 + rlwinm. r3, r4, 0, 0, 31 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000012345678 diff --git a/src/xenia/cpu/ppc/testing/instr_rlwnmx.s b/src/xenia/cpu/ppc/testing/instr_rlwnmx.s new file mode 100644 index 000000000..22fb332e6 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_rlwnmx.s @@ -0,0 +1,35 @@ +test_rlwnmx_1: + #_ REGISTER_IN r4 0x0000000012345678 + #_ REGISTER_IN r5 0x0000000000000008 + rlwnm. r3, r4, r5, 16, 23 + blr + #_ REGISTER_OUT r3 0x0000000000007800 + #_ REGISTER_OUT r4 0x0000000012345678 + #_ REGISTER_OUT r5 0x0000000000000008 + +test_rlwnmx_2: + #_ REGISTER_IN r4 0x0000000012345678 + #_ REGISTER_IN r5 0x0000000000000010 + rlwnm. r3, r4, r5, 8, 15 + blr + #_ REGISTER_OUT r3 0x0000000000780000 + #_ REGISTER_OUT r4 0x0000000012345678 + #_ REGISTER_OUT r5 0x0000000000000010 + +test_rlwnmx_3: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x0000000000000004 + rlwnm. r3, r4, r5, 20, 27 + blr + #_ REGISTER_OUT r3 0x0000000000000FF0 + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000004 + +test_rlwnmx_4: + #_ REGISTER_IN r4 0x0000000012345678 + #_ REGISTER_IN r5 0x0000000000000000 + rlwnm. r3, r4, r5, 0, 31 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000012345678 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_sldx.s b/src/xenia/cpu/ppc/testing/instr_sldx.s new file mode 100644 index 000000000..63a11d81d --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_sldx.s @@ -0,0 +1,35 @@ +test_sldx_1: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000004 + sld. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000010 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_sldx_2: + #_ REGISTER_IN r4 0x1234567890ABCDEF + #_ REGISTER_IN r5 0x0000000000000008 + sld. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x34567890ABCDEF00 + #_ REGISTER_OUT r4 0x1234567890ABCDEF + #_ REGISTER_OUT r5 0x0000000000000008 + +test_sldx_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000020 + sld. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFF00000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000020 + +test_sldx_4: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000000 + sld. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_slwx.s b/src/xenia/cpu/ppc/testing/instr_slwx.s new file mode 100644 index 000000000..4f8757c16 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_slwx.s @@ -0,0 +1,35 @@ +test_slwx_1: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000004 + slw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000010 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_slwx_2: + #_ REGISTER_IN r4 0x0000000012345678 + #_ REGISTER_IN r5 0x0000000000000008 + slw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000034567800 + #_ REGISTER_OUT r4 0x0000000012345678 + #_ REGISTER_OUT r5 0x0000000000000008 + +test_slwx_3: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x0000000000000010 + slw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFF0000 + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000010 + +test_slwx_4: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000000 + slw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_sradix.s b/src/xenia/cpu/ppc/testing/instr_sradix.s new file mode 100644 index 000000000..479dcc10f --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_sradix.s @@ -0,0 +1,27 @@ +test_sradix_1: + #_ REGISTER_IN r4 0x0000000000000010 + sradi. r3, r4, 4 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000010 + +test_sradix_2: + #_ REGISTER_IN r4 0x8000000000000000 + sradi. r3, r4, 8 + blr + #_ REGISTER_OUT r3 0xFF80000000000000 + #_ REGISTER_OUT r4 0x8000000000000000 + +test_sradix_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + sradi. r3, r4, 16 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + +test_sradix_4: + #_ REGISTER_IN r4 0x0000000000000001 + sradi. r3, r4, 0 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_sradx.s b/src/xenia/cpu/ppc/testing/instr_sradx.s new file mode 100644 index 000000000..78215eb41 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_sradx.s @@ -0,0 +1,35 @@ +test_sradx_1: + #_ REGISTER_IN r4 0x0000000000000010 + #_ REGISTER_IN r5 0x0000000000000004 + srad. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000010 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_sradx_2: + #_ REGISTER_IN r4 0x8000000000000000 + #_ REGISTER_IN r5 0x0000000000000008 + srad. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFF80000000000000 + #_ REGISTER_OUT r4 0x8000000000000000 + #_ REGISTER_OUT r5 0x0000000000000008 + +test_sradx_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000020 + srad. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000020 + +test_sradx_4: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000000 + srad. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_srawix.s b/src/xenia/cpu/ppc/testing/instr_srawix.s new file mode 100644 index 000000000..16d6f6d4e --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_srawix.s @@ -0,0 +1,27 @@ +test_srawix_1: + #_ REGISTER_IN r4 0x0000000000000010 + srawi. r3, r4, 4 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000010 + +test_srawix_2: + #_ REGISTER_IN r4 0x0000000080000000 + srawi. r3, r4, 8 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFF800000 + #_ REGISTER_OUT r4 0x0000000080000000 + +test_srawix_3: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + srawi. r3, r4, 16 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + +test_srawix_4: + #_ REGISTER_IN r4 0x0000000000000001 + srawi. r3, r4, 0 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 diff --git a/src/xenia/cpu/ppc/testing/instr_srawx.s b/src/xenia/cpu/ppc/testing/instr_srawx.s new file mode 100644 index 000000000..6efe5a238 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_srawx.s @@ -0,0 +1,35 @@ +test_srawx_1: + #_ REGISTER_IN r4 0x0000000000000010 + #_ REGISTER_IN r5 0x0000000000000004 + sraw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000010 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_srawx_2: + #_ REGISTER_IN r4 0x0000000080000000 + #_ REGISTER_IN r5 0x0000000000000008 + sraw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFF800000 + #_ REGISTER_OUT r4 0x0000000080000000 + #_ REGISTER_OUT r5 0x0000000000000008 + +test_srawx_3: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x0000000000000010 + sraw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000010 + +test_srawx_4: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000000 + sraw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_srdx.s b/src/xenia/cpu/ppc/testing/instr_srdx.s new file mode 100644 index 000000000..c4a7307cb --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_srdx.s @@ -0,0 +1,35 @@ +test_srdx_1: + #_ REGISTER_IN r4 0x0000000000000010 + #_ REGISTER_IN r5 0x0000000000000004 + srd. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000010 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_srdx_2: + #_ REGISTER_IN r4 0x1234567890ABCDEF + #_ REGISTER_IN r5 0x0000000000000008 + srd. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x001234567890ABCD + #_ REGISTER_OUT r4 0x1234567890ABCDEF + #_ REGISTER_OUT r5 0x0000000000000008 + +test_srdx_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0x0000000000000020 + srd. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000020 + +test_srdx_4: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000000 + srd. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_srwx.s b/src/xenia/cpu/ppc/testing/instr_srwx.s new file mode 100644 index 000000000..f423954f5 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_srwx.s @@ -0,0 +1,35 @@ +test_srwx_1: + #_ REGISTER_IN r4 0x0000000000000010 + #_ REGISTER_IN r5 0x0000000000000004 + srw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000010 + #_ REGISTER_OUT r5 0x0000000000000004 + +test_srwx_2: + #_ REGISTER_IN r4 0x0000000012345678 + #_ REGISTER_IN r5 0x0000000000000008 + srw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000123456 + #_ REGISTER_OUT r4 0x0000000012345678 + #_ REGISTER_OUT r5 0x0000000000000008 + +test_srwx_3: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 0x0000000000000010 + srw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000000000000FFFF + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + #_ REGISTER_OUT r5 0x0000000000000010 + +test_srwx_4: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0x0000000000000000 + srw. r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0000000000000001 + #_ REGISTER_OUT r5 0x0000000000000000 diff --git a/src/xenia/cpu/ppc/testing/instr_stb.s b/src/xenia/cpu/ppc/testing/instr_stb.s new file mode 100644 index 000000000..8377aca41 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stb.s @@ -0,0 +1,53 @@ +test_stb_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x00000000000000AB + #_ REGISTER_IN r4 0x0000000010001000 + stb r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x00000000000000AB + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001000 AB000000 + +test_stb_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x00000000000000CD + #_ REGISTER_IN r4 0x0000000010001000 + stb r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x00000000000000CD + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001004 CD000000 + +test_stbu_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x00000000000000EF + #_ REGISTER_IN r4 0x0000000010001000 + stbu r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x00000000000000EF + #_ REGISTER_OUT r4 0x0000000010001004 + #_ MEMORY_OUT 10001004 EF000000 + +test_stbx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000000000012 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000003 + stbx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000012 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000003 + #_ MEMORY_OUT 10001000 00000012 + +test_stbux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000000000034 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000005 + stbux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000034 + #_ REGISTER_OUT r4 0x0000000010001005 + #_ REGISTER_OUT r5 0x0000000000000005 + #_ MEMORY_OUT 10001004 00340000 diff --git a/src/xenia/cpu/ppc/testing/instr_std.s b/src/xenia/cpu/ppc/testing/instr_std.s new file mode 100644 index 000000000..4fe177ef6 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_std.s @@ -0,0 +1,53 @@ +test_std_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0xABCDEF1234567890 + #_ REGISTER_IN r4 0x0000000010001000 + std r3, 0(r4) + blr + #_ REGISTER_OUT r3 0xABCDEF1234567890 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001000 ABCDEF12 34567890 + +test_std_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x123456789ABCDEF0 + #_ REGISTER_IN r4 0x0000000010001000 + std r3, 8(r4) + blr + #_ REGISTER_OUT r3 0x123456789ABCDEF0 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001008 12345678 9ABCDEF0 + +test_stdu_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0xFEDCBA9876543210 + #_ REGISTER_IN r4 0x0000000010001000 + stdu r3, 8(r4) + blr + #_ REGISTER_OUT r3 0xFEDCBA9876543210 + #_ REGISTER_OUT r4 0x0000000010001008 + #_ MEMORY_OUT 10001008 FEDCBA98 76543210 + +test_stdx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x1122334455667788 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + stdx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x1122334455667788 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000008 + #_ MEMORY_OUT 10001008 11223344 55667788 + +test_stdux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x99AABBCCDDEEFF00 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000010 + stdux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x99AABBCCDDEEFF00 + #_ REGISTER_OUT r4 0x0000000010001010 + #_ REGISTER_OUT r5 0x0000000000000010 + #_ MEMORY_OUT 10001010 99AABBCC DDEEFF00 diff --git a/src/xenia/cpu/ppc/testing/instr_stfd.s b/src/xenia/cpu/ppc/testing/instr_stfd.s new file mode 100644 index 000000000..bc59f9f42 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stfd.s @@ -0,0 +1,53 @@ +test_stfd_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x3FF0000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + stfd f3, 0(r4) + blr + #_ REGISTER_OUT f3 0x3FF0000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001000 3FF00000 00000000 + +test_stfd_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x4000000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + stfd f3, 8(r4) + blr + #_ REGISTER_OUT f3 0x4000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001008 40000000 00000000 + +test_stfdu_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x4008000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + stfdu f3, 8(r4) + blr + #_ REGISTER_OUT f3 0x4008000000000000 + #_ REGISTER_OUT r4 0x0000000010001008 + #_ MEMORY_OUT 10001008 40080000 00000000 + +test_stfdx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x4010000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + stfdx f3, r4, r5 + blr + #_ REGISTER_OUT f3 0x4010000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000008 + #_ MEMORY_OUT 10001008 40100000 00000000 + +test_stfdux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x4014000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + stfdux f3, r4, r5 + blr + #_ REGISTER_OUT f3 0x4014000000000000 + #_ REGISTER_OUT r4 0x0000000010001008 + #_ REGISTER_OUT r5 0x0000000000000008 + #_ MEMORY_OUT 10001008 40140000 00000000 diff --git a/src/xenia/cpu/ppc/testing/instr_stfs.s b/src/xenia/cpu/ppc/testing/instr_stfs.s new file mode 100644 index 000000000..c9d4b15cd --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stfs.s @@ -0,0 +1,53 @@ +test_stfs_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x3FF0000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + stfs f3, 0(r4) + blr + #_ REGISTER_OUT f3 0x3FF0000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001000 3F800000 + +test_stfs_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x4000000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + stfs f3, 4(r4) + blr + #_ REGISTER_OUT f3 0x4000000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001004 40000000 + +test_stfsu_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x4008000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + stfsu f3, 4(r4) + blr + #_ REGISTER_OUT f3 0x4008000000000000 + #_ REGISTER_OUT r4 0x0000000010001004 + #_ MEMORY_OUT 10001004 40400000 + +test_stfsx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x4010000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + stfsx f3, r4, r5 + blr + #_ REGISTER_OUT f3 0x4010000000000000 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + #_ MEMORY_OUT 10001004 40800000 + +test_stfsux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN f3 0x4014000000000000 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + stfsux f3, r4, r5 + blr + #_ REGISTER_OUT f3 0x4014000000000000 + #_ REGISTER_OUT r4 0x0000000010001004 + #_ REGISTER_OUT r5 0x0000000000000004 + #_ MEMORY_OUT 10001004 40A00000 diff --git a/src/xenia/cpu/ppc/testing/instr_sth.s b/src/xenia/cpu/ppc/testing/instr_sth.s new file mode 100644 index 000000000..5924e69e4 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_sth.s @@ -0,0 +1,53 @@ +test_sth_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x000000000000ABCD + #_ REGISTER_IN r4 0x0000000010001000 + sth r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x000000000000ABCD + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001000 ABCD0000 + +test_sth_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000000001234 + #_ REGISTER_IN r4 0x0000000010001000 + sth r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000000001234 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001004 12340000 + +test_sthu_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000000005678 + #_ REGISTER_IN r4 0x0000000010001000 + sthu r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000000005678 + #_ REGISTER_OUT r4 0x0000000010001004 + #_ MEMORY_OUT 10001004 56780000 + +test_sthx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000000009ABC + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000002 + sthx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000009ABC + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000002 + #_ MEMORY_OUT 10001000 00009ABC + +test_sthux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x000000000000DEF0 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000006 + sthux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000000000000DEF0 + #_ REGISTER_OUT r4 0x0000000010001006 + #_ REGISTER_OUT r5 0x0000000000000006 + #_ MEMORY_OUT 10001004 0000DEF0 diff --git a/src/xenia/cpu/ppc/testing/instr_sthbrx.s b/src/xenia/cpu/ppc/testing/instr_sthbrx.s new file mode 100644 index 000000000..a70d4cb46 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_sthbrx.s @@ -0,0 +1,71 @@ +test_sthbrx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x000000000000ABCD + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + sthbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000000000000ABCD + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + #_ MEMORY_OUT 10001000 CDAB0000 + +test_sthbrx_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000000001234 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + sthbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000001234 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + #_ MEMORY_OUT 10001004 34120000 + +test_stwbrx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x00000000ABCDEF12 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + stwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000ABCDEF12 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + #_ MEMORY_OUT 10001000 12EFCDAB + +test_stwbrx_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000012345678 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + stwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + #_ MEMORY_OUT 10001004 78563412 + +test_stdbrx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0xABCDEF1234567890 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + stdbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xABCDEF1234567890 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + #_ MEMORY_OUT 10001000 90785634 12EFCDAB + +test_stdbrx_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x123456789ABCDEF0 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + stdbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x123456789ABCDEF0 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + #_ MEMORY_OUT 10001004 F0DEBC9A 78563412 diff --git a/src/xenia/cpu/ppc/testing/instr_stmw.s b/src/xenia/cpu/ppc/testing/instr_stmw.s new file mode 100644 index 000000000..2db14c3c1 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stmw.s @@ -0,0 +1,25 @@ +test_stmw_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r30 0x0000000000000001 + #_ REGISTER_IN r31 0x0000000000000002 + stmw r30, 0(r4) + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r30 0x0000000000000001 + #_ REGISTER_OUT r31 0x0000000000000002 + #_ MEMORY_OUT 10001000 00000001 00000002 + +test_stmw_2: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r4 0x0000000010000FF8 + #_ REGISTER_IN r29 0x000000000000000A + #_ REGISTER_IN r30 0x000000000000000B + #_ REGISTER_IN r31 0x000000000000000C + stmw r29, 8(r4) + blr + #_ REGISTER_OUT r4 0x0000000010000FF8 + #_ REGISTER_OUT r29 0x000000000000000A + #_ REGISTER_OUT r30 0x000000000000000B + #_ REGISTER_OUT r31 0x000000000000000C + #_ MEMORY_OUT 10001000 0000000A 0000000B 0000000C diff --git a/src/xenia/cpu/ppc/testing/instr_stvewx128.s b/src/xenia/cpu/ppc/testing/instr_stvewx128.s new file mode 100644 index 000000000..bfb16f200 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stvewx128.s @@ -0,0 +1,43 @@ +test_stvewx128_1: + # Store vector element word 128 - stores 4 bytes at aligned address + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + stvewx128 v3, r0, r4 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001000 01020304 + +test_stvewx128_2: + # Store to second element position + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001004 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + stvewx128 v3, r0, r4 + blr + #_ REGISTER_OUT r4 0x0000000010001004 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001004 05060708 + +test_stvewx128_3: + # Store to third element position + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001008 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + stvewx128 v3, r0, r4 + blr + #_ REGISTER_OUT r4 0x0000000010001008 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001008 090A0B0C + +test_stvewx128_4: + # Store to fourth element position + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x000000001000100C + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + stvewx128 v3, r0, r4 + blr + #_ REGISTER_OUT r4 0x000000001000100C + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 1000100C 0D0E0F10 diff --git a/src/xenia/cpu/ppc/testing/instr_stvlx128.s b/src/xenia/cpu/ppc/testing/instr_stvlx128.s new file mode 100644 index 000000000..a3d42dbf3 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stvlx128.s @@ -0,0 +1,22 @@ +test_stvlx128_1: + # Store vector left 128 - stores from EA to high bytes + # EA=0x10001077, aligns to 0x10001070, offset=7 + #_ MEMORY_IN 0x0000000010001070 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001077 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + stvlx128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001077 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001077 010203040506070809 + +test_stvlx128_2: + # Test aligned address (stores full vector) + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + stvlx128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + #_ MEMORY_OUT 10001000 AABBCCDDEEFF00112233445566778899 diff --git a/src/xenia/cpu/ppc/testing/instr_stvlxl128.s b/src/xenia/cpu/ppc/testing/instr_stvlxl128.s new file mode 100644 index 000000000..83dc2a5b9 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stvlxl128.s @@ -0,0 +1,22 @@ +test_stvlxl128_1: + # Store vector left 128 with cache hint + # EA=0x10001077, aligns to 0x10001070, offset=7 + #_ MEMORY_IN 0x0000000010001070 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001077 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + stvlxl128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001077 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001077 010203040506070809 + +test_stvlxl128_2: + # Test aligned address + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + stvlxl128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + #_ MEMORY_OUT 10001000 AABBCCDDEEFF00112233445566778899 diff --git a/src/xenia/cpu/ppc/testing/instr_stvrx128.s b/src/xenia/cpu/ppc/testing/instr_stvrx128.s new file mode 100644 index 000000000..60f2898b7 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stvrx128.s @@ -0,0 +1,21 @@ +test_stvrx128_1: + # Store vector right 128 - stores from EA to low bytes + # EA=0x10001077, aligns to 0x10001070, offset=7 + #_ MEMORY_IN 0x0000000010001070 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001077 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + stvrx128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001077 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001070 0A0B0C0D0E0F10 + +test_stvrx128_2: + # Test aligned address (stores nothing per AltiVec spec) + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + stvrx128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT v3 [AABBCCDD, EEFF0011, 22334455, 66778899] diff --git a/src/xenia/cpu/ppc/testing/instr_stvrxl128.s b/src/xenia/cpu/ppc/testing/instr_stvrxl128.s new file mode 100644 index 000000000..245646732 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stvrxl128.s @@ -0,0 +1,21 @@ +test_stvrxl128_1: + # Store vector right 128 with cache hint + # EA=0x10001077, aligns to 0x10001070, offset=7 + #_ MEMORY_IN 0x0000000010001070 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001077 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + stvrxl128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001077 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001070 0A0B0C0D0E0F10 + +test_stvrxl128_2: + # Test aligned address (stores nothing per AltiVec spec) + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + stvrxl128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT v3 [AABBCCDD, EEFF0011, 22334455, 66778899] diff --git a/src/xenia/cpu/ppc/testing/instr_stvx.s b/src/xenia/cpu/ppc/testing/instr_stvx.s new file mode 100644 index 000000000..7bdb9b7af --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stvx.s @@ -0,0 +1,40 @@ +test_stvx_1: + # Basic 16-byte aligned store + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + li r5, 0 + stvx v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001000 0102030405060708090A0B0C0D0E0F10 + +test_stvx_2: + # Test with offset + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ MEMORY_IN 0x0000000010001010 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + li r5, 16 + stvx v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 16 + #_ REGISTER_OUT v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + #_ MEMORY_OUT 10001010 AABBCCDDEEFF00112233445566778899 + +test_stvx_3: + # Test unaligned address (should mask to 16-byte boundary) + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [11223344, 55667788, 99AABBCC, DDEEFF00] + li r5, 13 # unaligned + stvx v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 13 + #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00] + # Should store to aligned address 0x10001000 + #_ MEMORY_OUT 10001000 112233445566778899AABBCCDDEEFF00 diff --git a/src/xenia/cpu/ppc/testing/instr_stvx128.s b/src/xenia/cpu/ppc/testing/instr_stvx128.s new file mode 100644 index 000000000..074ae0be0 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stvx128.s @@ -0,0 +1,51 @@ +test_stvx128_1: + # Basic 128-bit aligned store + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + stvx128 v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001000 0102030405060708090A0B0C0D0E0F10 + +test_stvx128_2: + # Test with offset + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ MEMORY_IN 0x0000000010001010 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + li r5, 16 + stvx128 v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 16 + #_ REGISTER_OUT v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + #_ MEMORY_OUT 10001010 AABBCCDDEEFF00112233445566778899 + +test_stvx128_3: + # Test unaligned address (should mask to 16-byte boundary) + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [11223344, 55667788, 99AABBCC, DDEEFF00] + li r5, 7 # unaligned + stvx128 v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 7 + #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00] + # Should store to aligned address 0x10001000 + #_ MEMORY_OUT 10001000 112233445566778899AABBCCDDEEFF00 + +test_stvx128_4: + # Test with high register (v100+) + # NOTE: High registers (v100+) not supported by binutils mnemonics, must use .long + # TODO: Opcode 0x1C8401C3 appears incorrect - corrupts r4 and doesn't store + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v100 [DEADBEEF, CAFEBABE, 12345678, 9ABCDEF0] + .long 0x1C8401C3 # stvx128 v100, r4, r0 + blr + #_ REGISTER_OUT r4 0x0000001C301C3000 + #_ REGISTER_OUT v100 [DEADBEEF, CAFEBABE, 12345678, 9ABCDEF0] + #_ MEMORY_OUT 10001000 000CCC00CC00CC00CC00CC00CC00CC00 diff --git a/src/xenia/cpu/ppc/testing/instr_stvxl.s b/src/xenia/cpu/ppc/testing/instr_stvxl.s new file mode 100644 index 000000000..b782a1756 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stvxl.s @@ -0,0 +1,26 @@ +test_stvxl_1: + # Store vector with cache hint (least recently used) + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + li r5, 0 + stvxl v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001000 0102030405060708090A0B0C0D0E0F10 + +test_stvxl_2: + # Test with offset + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ MEMORY_IN 0x0000000010001010 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + li r5, 16 + stvxl v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 16 + #_ REGISTER_OUT v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + #_ MEMORY_OUT 10001010 AABBCCDDEEFF00112233445566778899 diff --git a/src/xenia/cpu/ppc/testing/instr_stvxl128.s b/src/xenia/cpu/ppc/testing/instr_stvxl128.s new file mode 100644 index 000000000..2d7eaa19c --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stvxl128.s @@ -0,0 +1,26 @@ +test_stvxl128_1: + # Store vector 128 with cache hint + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + li r5, 0 + stvxl128 v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ MEMORY_OUT 10001000 0102030405060708090A0B0C0D0E0F10 + +test_stvxl128_2: + # Test with offset + #_ MEMORY_IN 0x0000000010001000 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ MEMORY_IN 0x0000000010001010 [CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC, CC] + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + li r5, 16 + stvxl128 v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 16 + #_ REGISTER_OUT v3 [AABBCCDD, EEFF0011, 22334455, 66778899] + #_ MEMORY_OUT 10001010 AABBCCDDEEFF00112233445566778899 diff --git a/src/xenia/cpu/ppc/testing/instr_stw.s b/src/xenia/cpu/ppc/testing/instr_stw.s new file mode 100644 index 000000000..f010f51d4 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stw.s @@ -0,0 +1,53 @@ +test_stw_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x00000000ABCDEF12 + #_ REGISTER_IN r4 0x0000000010001000 + stw r3, 0(r4) + blr + #_ REGISTER_OUT r3 0x00000000ABCDEF12 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001000 ABCDEF12 + +test_stw_offset: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000012345678 + #_ REGISTER_IN r4 0x0000000010001000 + stw r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ MEMORY_OUT 10001004 12345678 + +test_stwu_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x000000009ABCDEF0 + #_ REGISTER_IN r4 0x0000000010001000 + stwu r3, 4(r4) + blr + #_ REGISTER_OUT r3 0x000000009ABCDEF0 + #_ REGISTER_OUT r4 0x0000000010001004 + #_ MEMORY_OUT 10001004 9ABCDEF0 + +test_stwx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x00000000FEDCBA98 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000004 + stwx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FEDCBA98 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000004 + #_ MEMORY_OUT 10001004 FEDCBA98 + +test_stwux_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000011223344 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000008 + stwux r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000011223344 + #_ REGISTER_OUT r4 0x0000000010001008 + #_ REGISTER_OUT r5 0x0000000000000008 + #_ MEMORY_OUT 10001008 11223344 diff --git a/src/xenia/cpu/ppc/testing/instr_stwbrx.s b/src/xenia/cpu/ppc/testing/instr_stwbrx.s new file mode 100644 index 000000000..6e7c99c10 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stwbrx.s @@ -0,0 +1,35 @@ +test_stwbrx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000012345678 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0 + stwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0 + #_ MEMORY_OUT 10001000 78563412 + +test_stwbrx_2: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x00000000ABCDEF01 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 4 + stwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000ABCDEF01 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 4 + #_ MEMORY_OUT 10001004 01EFCDAB + +test_stwbrx_3: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x00000000FFFEFDFC + #_ REGISTER_IN r4 0 + #_ REGISTER_IN r5 0x0000000010001000 + stwbrx r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFEFDFC + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 0x0000000010001000 + #_ MEMORY_OUT 10001000 FCFDFEFF diff --git a/src/xenia/cpu/ppc/testing/instr_stwcx.s b/src/xenia/cpu/ppc/testing/instr_stwcx.s new file mode 100644 index 000000000..b39095d2d --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_stwcx.s @@ -0,0 +1,63 @@ +test_stwcx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x00000000ABCDEF12 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + # First do lwarx to set reservation + lwarx r6, r4, r5 + # Then do stwcx to store conditionally + stwcx. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x00000000ABCDEF12 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + #_ REGISTER_OUT r12 0x20000000 + #_ MEMORY_OUT 10001000 ABCDEF12 + +test_stwcx_fail: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x0000000012345678 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + # stwcx without prior lwarx should fail + stwcx. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x0000000012345678 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + #_ REGISTER_OUT r12 0x00000000 + #_ MEMORY_OUT 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] + +test_stdcx_1: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0xABCDEF1234567890 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + # First do ldarx to set reservation + ldarx r6, r4, r5 + # Then do stdcx to store conditionally + stdcx. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xABCDEF1234567890 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + #_ REGISTER_OUT r12 0x20000000 + #_ MEMORY_OUT 10001000 ABCDEF12 34567890 + +test_stdcx_fail: + #_ MEMORY_IN 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00] + #_ REGISTER_IN r3 0x123456789ABCDEF0 + #_ REGISTER_IN r4 0x0000000010001000 + #_ REGISTER_IN r5 0x0000000000000000 + # stdcx without prior ldarx should fail + stdcx. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x123456789ABCDEF0 + #_ REGISTER_OUT r4 0x0000000010001000 + #_ REGISTER_OUT r5 0x0000000000000000 + #_ REGISTER_OUT r12 0x00000000 + #_ MEMORY_OUT 0x0000000010001000 [00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00] diff --git a/src/xenia/cpu/ppc/testing/instr_subfx.s b/src/xenia/cpu/ppc/testing/instr_subfx.s new file mode 100644 index 000000000..559ac7157 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_subfx.s @@ -0,0 +1,90 @@ +test_subfx_1: + #_ REGISTER_IN r4 0x0000000000003000 + #_ REGISTER_IN r5 0x0000000000001000 + subf. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFE000 + #_ REGISTER_OUT r12 0x0000000080000000 + +test_subfx_1_constant: + li r4, 0x3000 + li r5, 0x1000 + subf. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFE000 + #_ REGISTER_OUT r12 0x0000000080000000 + +test_subfx_underflow: + #_ REGISTER_IN r4 0x8000000000000000 + #_ REGISTER_IN r5 0x0000000000000001 + subf. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0x8000000000000001 + #_ REGISTER_OUT r12 0x0000000040000000 + +test_subfx_negative: + #_ REGISTER_IN r4 0x0000000000000001 + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + subf. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r12 0x0000000080000000 + +test_subfcx_1: + #_ REGISTER_IN r4 0x0000000000003000 + #_ REGISTER_IN r5 0x0000000000001000 + subfc. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFE000 + #_ REGISTER_OUT r12 0x0000000080000000 + +test_subfcx_borrow: + #_ REGISTER_IN r4 0x0000000000000002 + #_ REGISTER_IN r5 0x0000000000000001 + subfc. r3, r4, r5 + mfcr r12 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r12 0x0000000080000000 + +test_subfex_1: + #_ REGISTER_IN r4 0x0000000000003000 + #_ REGISTER_IN r5 0x0000000000001000 + #_ REGISTER_IN r0 0x0000000000000000 + mtxer r0 + subfe. r3, r4, r5 + mfcr r12 + mfxer r6 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFDFFF + #_ REGISTER_OUT r6 0x0000000000000000 + #_ REGISTER_OUT r12 0x0000000080000000 + +test_subfmex_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r0 0x0000000000000000 + mtxer r0 + subfme. r3, r4 + mfcr r12 + mfxer r6 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFEFFE + #_ REGISTER_OUT r6 0x0000000020000000 + #_ REGISTER_OUT r12 0x0000000080000000 + +test_subfzex_1: + #_ REGISTER_IN r4 0x0000000000001000 + #_ REGISTER_IN r0 0x0000000000000000 + mtxer r0 + subfze. r3, r4 + mfcr r12 + mfxer r6 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFEFFF + #_ REGISTER_OUT r6 0x0000000000000000 + #_ REGISTER_OUT r12 0x0000000080000000 diff --git a/src/xenia/cpu/ppc/testing/instr_sync.s b/src/xenia/cpu/ppc/testing/instr_sync.s new file mode 100644 index 000000000..dfe6bae25 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_sync.s @@ -0,0 +1,13 @@ +test_sync_1: + #_ REGISTER_IN r3 0x0000000000000001 + sync + blr + #_ REGISTER_OUT r3 0x0000000000000001 + +test_sync_2: + #_ REGISTER_IN r4 0x0000000012345678 + #_ REGISTER_IN r5 0xABCDEF0123456789 + sync + blr + #_ REGISTER_OUT r4 0x0000000012345678 + #_ REGISTER_OUT r5 0xABCDEF0123456789 diff --git a/src/xenia/cpu/ppc/testing/instr_vcfpsxws128.s b/src/xenia/cpu/ppc/testing/instr_vcfpsxws128.s new file mode 100644 index 000000000..6bba5d5e0 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vcfpsxws128.s @@ -0,0 +1,63 @@ +test_vcfpsxws128_1: + # Convert 0.0 to signed integer + #_ REGISTER_IN v0 [00000000, 00000000, 00000000, 00000000] + vcfpsxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + +test_vcfpsxws128_2: + # Convert 1.0 to signed integer + #_ REGISTER_IN v0 [3F800000, 3F800000, 3F800000, 3F800000] + vcfpsxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] + +test_vcfpsxws128_3: + # Convert -1.0 to signed integer + #_ REGISTER_IN v0 [BF800000, BF800000, BF800000, BF800000] + vcfpsxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcfpsxws128_4: + # Convert 2.0 to signed integer + #_ REGISTER_IN v0 [40000000, 40000000, 40000000, 40000000] + vcfpsxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002] + +test_vcfpsxws128_5: + # Convert 100.5 (should truncate to 100) + #_ REGISTER_IN v0 [42C90000, 42C90000, 42C90000, 42C90000] + vcfpsxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [42C90000, 42C90000, 42C90000, 42C90000] + #_ REGISTER_OUT v3 [00000064, 00000064, 00000064, 00000064] + +test_vcfpsxws128_6: + # Convert max positive (overflow to 0x7FFFFFFF) + #_ REGISTER_IN v0 [4F000000, 4F000000, 4F000000, 4F000000] + vcfpsxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [4F000000, 4F000000, 4F000000, 4F000000] + #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] + +test_vcfpsxws128_7: + # Convert positive infinity (overflow to 0x7FFFFFFF) + #_ REGISTER_IN v0 [7F800000, 7F800000, 7F800000, 7F800000] + vcfpsxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [7F800000, 7F800000, 7F800000, 7F800000] + #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] + +test_vcfpsxws128_8: + # Convert negative infinity (overflow to 0x80000000) + #_ REGISTER_IN v0 [FF800000, FF800000, FF800000, FF800000] + vcfpsxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [FF800000, FF800000, FF800000, FF800000] + #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vcfpuxws128.s b/src/xenia/cpu/ppc/testing/instr_vcfpuxws128.s new file mode 100644 index 000000000..32943fffb --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vcfpuxws128.s @@ -0,0 +1,63 @@ +test_vcfpuxws128_1: + # Convert 0.0 to unsigned integer + #_ REGISTER_IN v0 [00000000, 00000000, 00000000, 00000000] + vcfpuxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + +test_vcfpuxws128_2: + # Convert 1.0 to unsigned integer + #_ REGISTER_IN v0 [3F800000, 3F800000, 3F800000, 3F800000] + vcfpuxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] + +test_vcfpuxws128_3: + # Convert negative value (clamp to 0) + #_ REGISTER_IN v0 [BF800000, BF800000, BF800000, BF800000] + vcfpuxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + +test_vcfpuxws128_4: + # Convert 2.0 to unsigned integer + #_ REGISTER_IN v0 [40000000, 40000000, 40000000, 40000000] + vcfpuxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002] + +test_vcfpuxws128_5: + # Convert 100.5 (should truncate to 100) + #_ REGISTER_IN v0 [42C90000, 42C90000, 42C90000, 42C90000] + vcfpuxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [42C90000, 42C90000, 42C90000, 42C90000] + #_ REGISTER_OUT v3 [00000064, 00000064, 00000064, 00000064] + +test_vcfpuxws128_6: + # Convert large value (2^32 overflow to 0xFFFFFFFF) + #_ REGISTER_IN v0 [4F800000, 4F800000, 4F800000, 4F800000] + vcfpuxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [4F800000, 4F800000, 4F800000, 4F800000] + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcfpuxws128_7: + # Convert positive infinity (overflow to 0xFFFFFFFF) + #_ REGISTER_IN v0 [7F800000, 7F800000, 7F800000, 7F800000] + vcfpuxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [7F800000, 7F800000, 7F800000, 7F800000] + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcfpuxws128_8: + # Convert negative infinity (clamp to 0) + #_ REGISTER_IN v0 [FF800000, FF800000, FF800000, FF800000] + vcfpuxws128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [FF800000, FF800000, FF800000, FF800000] + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpequw128.s b/src/xenia/cpu/ppc/testing/instr_vcmpequw128.s new file mode 100644 index 000000000..52dd8398b --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vcmpequw128.s @@ -0,0 +1,59 @@ +test_vcmpequw128_1: + # All elements equal (zeros) + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vcmpequw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcmpequw128_2: + # All elements equal (ones) + #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + vcmpequw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcmpequw128_3: + # No elements equal + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] + vcmpequw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vcmpequw128_4: + # All elements equal (mixed values) + #_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788] + #_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667788] + vcmpequw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788] + #_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667788] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcmpequw128_5: + # Last element different + #_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788] + #_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667789] + vcmpequw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788] + #_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667789] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, 00000000] + +test_vcmpequw128_6: + # First element different + #_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004] + #_ REGISTER_IN v4 [00000000, 00000002, 00000003, 00000004] + vcmpequw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004] + #_ REGISTER_OUT v4 [00000000, 00000002, 00000003, 00000004] + #_ REGISTER_OUT v5 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF] diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgefp128.s b/src/xenia/cpu/ppc/testing/instr_vcmpgefp128.s new file mode 100644 index 000000000..b9bd85274 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vcmpgefp128.s @@ -0,0 +1,69 @@ +test_vcmpgefp128_1: + # All elements v3 >= v4 (2.0 >= 1.0) + #_ REGISTER_IN v3 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + vcmpgefp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcmpgefp128_2: + # All elements equal (1.0 >= 1.0) + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + vcmpgefp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcmpgefp128_3: + # All elements v3 < v4 (1.0 < 2.0) + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000] + vcmpgefp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vcmpgefp128_4: + # 0.0 >= -1.0 + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000] + vcmpgefp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcmpgefp128_5: + # -2.0 < -1.0 + #_ REGISTER_IN v3 [C0000000, C0000000, C0000000, C0000000] + #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000] + vcmpgefp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000] + #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vcmpgefp128_6: + # Mixed: [1.0>=1.0, 2.0>=1.0, 3.0>=3.0, 4.0<5.0] + #_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 40400000, 40A00000] + vcmpgefp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 40400000, 40A00000] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, 00000000] + +test_vcmpgefp128_7: + # -0.0 and +0.0 + #_ REGISTER_IN v3 [80000000, 00000000, 00000000, 80000000] + #_ REGISTER_IN v4 [00000000, 80000000, 00000000, 80000000] + vcmpgefp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [80000000, 00000000, 00000000, 80000000] + #_ REGISTER_OUT v4 [00000000, 80000000, 00000000, 80000000] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgtfp128.s b/src/xenia/cpu/ppc/testing/instr_vcmpgtfp128.s new file mode 100644 index 000000000..1db57b00d --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vcmpgtfp128.s @@ -0,0 +1,69 @@ +test_vcmpgtfp128_1: + # All elements v3 > v4 (2.0 > 1.0) + #_ REGISTER_IN v3 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + vcmpgtfp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcmpgtfp128_2: + # All elements equal (1.0 == 1.0, not >) + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + vcmpgtfp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vcmpgtfp128_3: + # All elements v3 < v4 (1.0 < 2.0) + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000] + vcmpgtfp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vcmpgtfp128_4: + # 0.0 > -1.0 + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000] + vcmpgtfp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + +test_vcmpgtfp128_5: + # -2.0 < -1.0 + #_ REGISTER_IN v3 [C0000000, C0000000, C0000000, C0000000] + #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000] + vcmpgtfp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000] + #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vcmpgtfp128_6: + # Mixed: [1.0==1.0, 2.0>1.0, 3.0==3.0, 4.0<5.0] + #_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 40400000, 40A00000] + vcmpgtfp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 40400000, 40A00000] + #_ REGISTER_OUT v5 [00000000, FFFFFFFF, 00000000, 00000000] + +test_vcmpgtfp128_7: + # -0.0 and +0.0 (equal, not >) + #_ REGISTER_IN v3 [00000000, 00000000, 80000000, 80000000] + #_ REGISTER_IN v4 [00000000, 80000000, 00000000, 80000000] + vcmpgtfp128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 80000000, 80000000] + #_ REGISTER_OUT v4 [00000000, 80000000, 00000000, 80000000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vcsxwfp128.s b/src/xenia/cpu/ppc/testing/instr_vcsxwfp128.s new file mode 100644 index 000000000..2c3660470 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vcsxwfp128.s @@ -0,0 +1,63 @@ +test_vcsxwfp128_1: + # Convert 0 to float + #_ REGISTER_IN v0 [00000000, 00000000, 00000000, 00000000] + vcsxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + +test_vcsxwfp128_2: + # Convert 1 to float (1.0) + #_ REGISTER_IN v0 [00000001, 00000001, 00000001, 00000001] + vcsxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000001, 00000001, 00000001, 00000001] + #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000] + +test_vcsxwfp128_3: + # Convert -1 to float (-1.0) + #_ REGISTER_IN v0 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + vcsxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v3 [BF800000, BF800000, BF800000, BF800000] + +test_vcsxwfp128_4: + # Convert 2 to float (2.0) + #_ REGISTER_IN v0 [00000002, 00000002, 00000002, 00000002] + vcsxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000002, 00000002, 00000002, 00000002] + #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000] + +test_vcsxwfp128_5: + # Convert 100 to float (100.0) + #_ REGISTER_IN v0 [00000064, 00000064, 00000064, 00000064] + vcsxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000064, 00000064, 00000064, 00000064] + #_ REGISTER_OUT v3 [42C80000, 42C80000, 42C80000, 42C80000] + +test_vcsxwfp128_6: + # Convert -100 to float (-100.0) + #_ REGISTER_IN v0 [FFFFFF9C, FFFFFF9C, FFFFFF9C, FFFFFF9C] + vcsxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [FFFFFF9C, FFFFFF9C, FFFFFF9C, FFFFFF9C] + #_ REGISTER_OUT v3 [C2C80000, C2C80000, C2C80000, C2C80000] + +test_vcsxwfp128_7: + # Convert max positive signed int (0x7FFFFFFF) + #_ REGISTER_IN v0 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] + vcsxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] + #_ REGISTER_OUT v3 [4F000000, 4F000000, 4F000000, 4F000000] + +test_vcsxwfp128_8: + # Convert min negative signed int (0x80000000) + #_ REGISTER_IN v0 [80000000, 80000000, 80000000, 80000000] + vcsxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [80000000, 80000000, 80000000, 80000000] + #_ REGISTER_OUT v3 [CF000000, CF000000, CF000000, CF000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vcuxwfp128.s b/src/xenia/cpu/ppc/testing/instr_vcuxwfp128.s new file mode 100644 index 000000000..e19b4ce8c --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vcuxwfp128.s @@ -0,0 +1,63 @@ +test_vcuxwfp128_1: + # Convert 0 to float + #_ REGISTER_IN v0 [00000000, 00000000, 00000000, 00000000] + vcuxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + +test_vcuxwfp128_2: + # Convert 1 to float (1.0) + #_ REGISTER_IN v0 [00000001, 00000001, 00000001, 00000001] + vcuxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000001, 00000001, 00000001, 00000001] + #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000] + +test_vcuxwfp128_3: + # Convert 2 to float (2.0) + #_ REGISTER_IN v0 [00000002, 00000002, 00000002, 00000002] + vcuxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000002, 00000002, 00000002, 00000002] + #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000] + +test_vcuxwfp128_4: + # Convert 100 to float (100.0) + #_ REGISTER_IN v0 [00000064, 00000064, 00000064, 00000064] + vcuxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000064, 00000064, 00000064, 00000064] + #_ REGISTER_OUT v3 [42C80000, 42C80000, 42C80000, 42C80000] + +test_vcuxwfp128_5: + # Convert 0x7FFFFFFF (as unsigned) + #_ REGISTER_IN v0 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] + vcuxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] + #_ REGISTER_OUT v3 [4F000000, 4F000000, 4F000000, 4F000000] + +test_vcuxwfp128_6: + # Convert 0x80000000 (as unsigned = 2^31) + #_ REGISTER_IN v0 [80000000, 80000000, 80000000, 80000000] + vcuxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [80000000, 80000000, 80000000, 80000000] + #_ REGISTER_OUT v3 [4F000000, 4F000000, 4F000000, 4F000000] + +test_vcuxwfp128_7: + # Convert max unsigned (0xFFFFFFFF = 2^32-1) + #_ REGISTER_IN v0 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + vcuxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] + #_ REGISTER_OUT v3 [4F800000, 4F800000, 4F800000, 4F800000] + +test_vcuxwfp128_8: + # Convert mixed values + #_ REGISTER_IN v0 [00000001, 00000002, 00000064, FFFFFFFF] + vcuxwfp128 v3, v0, 0 + blr + #_ REGISTER_OUT v0 [00000001, 00000002, 00000064, FFFFFFFF] + #_ REGISTER_OUT v3 [3F800000, 40000000, 42C80000, 4F800000] diff --git a/src/xenia/cpu/ppc/testing/instr_vexptefp128.s b/src/xenia/cpu/ppc/testing/instr_vexptefp128.s new file mode 100644 index 000000000..79e258d46 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vexptefp128.s @@ -0,0 +1,39 @@ +test_vexptefp128_1: + # 2^x estimate for x = [0.0, 1.0, 2.0, 3.0] = [1.0, 2.0, 4.0, 8.0] + #_ REGISTER_IN v4 [00000000, 3F800000, 40000000, 40400000] + vexptefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [00000000, 3F800000, 40000000, 40400000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40800000, 41000000] + +test_vexptefp128_2: + # 2^x estimate for negative x = [-1.0, -2.0, -3.0, -4.0] + #_ REGISTER_IN v4 [BF800000, C0000000, C0400000, C0800000] + vexptefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [BF800000, C0000000, C0400000, C0800000] + #_ REGISTER_OUT v5 [3F000000, 3E800000, 3E000000, 3D800000] + +test_vexptefp128_3: + # 2^x estimate for small x = [0.5, 0.25, 0.125, 0.0625] + #_ REGISTER_IN v4 [3F000000, 3E800000, 3E000000, 3D800000] + vexptefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F000000, 3E800000, 3E000000, 3D800000] + #_ REGISTER_OUT v5 [3FB504F3, 3F9837F0, 3F8B95C2, 3F85AAC3] + +test_vexptefp128_4: + # 2^x estimate for larger values + #_ REGISTER_IN v4 [40800000, 40A00000, 40C00000, 40E00000] + vexptefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [40800000, 40A00000, 40C00000, 40E00000] + #_ REGISTER_OUT v5 [41800000, 42000000, 42800000, 43000000] + +test_vexptefp128_5: + # 2^x for x = 0 (should always be 1.0) + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vexptefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 3F800000] diff --git a/src/xenia/cpu/ppc/testing/instr_vlogefp128.s b/src/xenia/cpu/ppc/testing/instr_vlogefp128.s new file mode 100644 index 000000000..9d9361498 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vlogefp128.s @@ -0,0 +1,39 @@ +test_vlogefp128_1: + # log2(x) estimate for x = [1.0, 2.0, 4.0, 8.0] = [0.0, 1.0, 2.0, 3.0] + #_ REGISTER_IN v4 [3F800000, 40000000, 40800000, 41000000] + vlogefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40800000, 41000000] + #_ REGISTER_OUT v5 [00000000, 3F800000, 40000000, 40400000] + +test_vlogefp128_2: + # log2(x) estimate for fractions: [0.5, 0.25, 0.125, 0.0625] = [-1.0, -2.0, -3.0, -4.0] + #_ REGISTER_IN v4 [3F000000, 3E800000, 3E000000, 3D800000] + vlogefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F000000, 3E800000, 3E000000, 3D800000] + #_ REGISTER_OUT v5 [BF800000, C0000000, C0400000, C0800000] + +test_vlogefp128_3: + # log2(x) estimate for larger values + #_ REGISTER_IN v4 [41800000, 42000000, 42800000, 43000000] + vlogefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [41800000, 42000000, 42800000, 43000000] + #_ REGISTER_OUT v5 [40800000, 40A00000, 40C00000, 40E00000] + +test_vlogefp128_4: + # log2(1.0) = 0.0 (should always be zero) + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + vlogefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vlogefp128_5: + # log2(x) for values slightly above 1.0 + #_ REGISTER_IN v4 [3FB504F3, 3FC00000, 3FD744FD, 3FECCCCD] + vlogefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3FB504F3, 3FC00000, 3FD744FD, 3FECCCCD] + #_ REGISTER_OUT v5 [3EFFFFFF, 3F15C01A, 3F400000, 3F6334DB] diff --git a/src/xenia/cpu/ppc/testing/instr_vmaddcfp128.s b/src/xenia/cpu/ppc/testing/instr_vmaddcfp128.s new file mode 100644 index 000000000..e8310368d --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vmaddcfp128.s @@ -0,0 +1,32 @@ +test_vmaddcfp128_1: + # Multiply-add conjugate (exact behavior TBD) + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v5 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v6 [3F800000, 3F800000, 3F800000, 3F800000] + vmaddcfp128 v3, v4, v3, v5 + blr + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v6 [3F800000, 3F800000, 3F800000, 3F800000] + +test_vmaddcfp128_2: + # Test with zero + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v5 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v6 [3F800000, 3F800000, 3F800000, 3F800000] + vmaddcfp128 v3, v4, v3, v5 + blr + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v6 [3F800000, 3F800000, 3F800000, 3F800000] + +test_vmaddcfp128_3: + # Test with negative values + #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_IN v5 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_IN v6 [40A00000, 40A00000, 40A00000, 40A00000] + vmaddcfp128 v3, v4, v3, v5 + blr + #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v6 [40A00000, 40A00000, 40A00000, 40A00000] diff --git a/src/xenia/cpu/ppc/testing/instr_vmaddfp128.s b/src/xenia/cpu/ppc/testing/instr_vmaddfp128.s new file mode 100644 index 000000000..e615f72e4 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vmaddfp128.s @@ -0,0 +1,54 @@ +test_vmaddfp128_1: + # v3 = (v4 * v5) + v3: (1.0 * 1.0) + 1.0 = 2.0 + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v5 [3F800000, 3F800000, 3F800000, 3F800000] + vmaddfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 3F800000] + +test_vmaddfp128_2: + # v3 = (v4 * v5) + v3: (5.0 * 5.0) + 1.0 = 26.0 + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [40A00000, 40A00000, 40A00000, 40A00000] + #_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000] + vmaddfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [41D00000, 41D00000, 41D00000, 41D00000] + #_ REGISTER_OUT v4 [40A00000, 40A00000, 40A00000, 40A00000] + #_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000] + +test_vmaddfp128_3: + # v3 = (v4 * v5) + v3: (2.0 * 3.0) + 4.0 = 10.0 + #_ REGISTER_IN v3 [40800000, 40800000, 40800000, 40800000] + #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_IN v5 [40400000, 40400000, 40400000, 40400000] + vmaddfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [41200000, 41200000, 41200000, 41200000] + #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v5 [40400000, 40400000, 40400000, 40400000] + +test_vmaddfp128_4: + # v3 = (v4 * v5) + v3: (0.0 * 100.0) + 5.0 = 5.0 + #_ REGISTER_IN v3 [40A00000, 40A00000, 40A00000, 40A00000] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v5 [42C80000, 42C80000, 42C80000, 42C80000] + vmaddfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [40A00000, 40A00000, 40A00000, 40A00000] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [42C80000, 42C80000, 42C80000, 42C80000] + +test_vmaddfp128_5: + # v3 = (v4 * v5) + v3: (-1.0 * 2.0) + 5.0 = 3.0 + #_ REGISTER_IN v3 [40A00000, 40A00000, 40A00000, 40A00000] + #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_IN v5 [40000000, 40000000, 40000000, 40000000] + vmaddfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [40400000, 40400000, 40400000, 40400000] + #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vmrghw128.s b/src/xenia/cpu/ppc/testing/instr_vmrghw128.s new file mode 100644 index 000000000..d96412ff8 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vmrghw128.s @@ -0,0 +1,8 @@ +test_vmrghw128_1: + #_ REGISTER_IN v3 [11111111, 22222222, 33333333, 44444444] + #_ REGISTER_IN v4 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + vmrghw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [11111111, 22222222, 33333333, 44444444] + #_ REGISTER_OUT v4 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + #_ REGISTER_OUT v5 [11111111, AAAAAAAA, 22222222, BBBBBBBB] diff --git a/src/xenia/cpu/ppc/testing/instr_vmrglw128.s b/src/xenia/cpu/ppc/testing/instr_vmrglw128.s new file mode 100644 index 000000000..e9962f9ac --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vmrglw128.s @@ -0,0 +1,8 @@ +test_vmrglw128_1: + #_ REGISTER_IN v3 [11111111, 22222222, 33333333, 44444444] + #_ REGISTER_IN v4 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + vmrglw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [11111111, 22222222, 33333333, 44444444] + #_ REGISTER_OUT v4 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + #_ REGISTER_OUT v5 [33333333, CCCCCCCC, 44444444, DDDDDDDD] diff --git a/src/xenia/cpu/ppc/testing/instr_vmulfp128.s b/src/xenia/cpu/ppc/testing/instr_vmulfp128.s new file mode 100644 index 000000000..21072d539 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vmulfp128.s @@ -0,0 +1,49 @@ +test_vmulfp128_1: + # 1.0 * 1.0 = 1.0 + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v5 [3F800000, 3F800000, 3F800000, 3F800000] + vmulfp128 v3, v4, v5 + blr + #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 3F800000] + +test_vmulfp128_2: + # 2.0 * 3.0 = 6.0 + #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_IN v5 [40400000, 40400000, 40400000, 40400000] + vmulfp128 v3, v4, v5 + blr + #_ REGISTER_OUT v3 [40C00000, 40C00000, 40C00000, 40C00000] + #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v5 [40400000, 40400000, 40400000, 40400000] + +test_vmulfp128_3: + # 0.0 * anything = 0.0 + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v5 [42C80000, 42C80000, 42C80000, 42C80000] + vmulfp128 v3, v4, v5 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [42C80000, 42C80000, 42C80000, 42C80000] + +test_vmulfp128_4: + # -1.0 * 2.0 = -2.0 + #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_IN v5 [40000000, 40000000, 40000000, 40000000] + vmulfp128 v3, v4, v5 + blr + #_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000] + #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000] + #_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000] + +test_vmulfp128_5: + # Mixed values + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_IN v5 [40000000, 40000000, 3F800000, 3F800000] + vmulfp128 v3, v4, v5 + blr + #_ REGISTER_OUT v3 [40000000, 40800000, 40400000, 40800000] + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [40000000, 40000000, 3F800000, 3F800000] diff --git a/src/xenia/cpu/ppc/testing/instr_vnmsubfp128.s b/src/xenia/cpu/ppc/testing/instr_vnmsubfp128.s new file mode 100644 index 000000000..1ea2a75cb --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vnmsubfp128.s @@ -0,0 +1,54 @@ +test_vnmsubfp128_1: + # v3 = -((v4 * v5) - v3): -((0.0 * 0.0) - 0.0) = -0.0 + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000] + vnmsubfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000] + #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] + +test_vnmsubfp128_2: + # v3 = -((v4 * v5) - v3): -((1.0 * 3.0) - 1.0) = -2.0 + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v5 [40400000, 40400000, 40400000, 40400000] + vnmsubfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000] + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [40400000, 40400000, 40400000, 40400000] + +test_vnmsubfp128_3: + # v3 = -((v4 * v5) - v3): -((5.0 * 5.0) - 1.0) = -24.0 + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [40A00000, 40A00000, 40A00000, 40A00000] + #_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000] + vnmsubfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [C1C00000, C1C00000, C1C00000, C1C00000] + #_ REGISTER_OUT v4 [40A00000, 40A00000, 40A00000, 40A00000] + #_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000] + +test_vnmsubfp128_4: + # v3 = -((v4 * v5) - v3): -((2.0 * 3.0) - 1.0) = -5.0 + #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_IN v5 [40400000, 40400000, 40400000, 40400000] + vnmsubfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [C0A00000, C0A00000, C0A00000, C0A00000] + #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_OUT v5 [40400000, 40400000, 40400000, 40400000] + +test_vnmsubfp128_5: + # v3 = -((v4 * v5) - v3): -((3.0 * 3.0) - 2.0) = -7.0 + #_ REGISTER_IN v3 [40000000, 40000000, 40000000, 40000000] + #_ REGISTER_IN v4 [40400000, 40400000, 40400000, 40400000] + #_ REGISTER_IN v5 [40400000, 40400000, 40400000, 40400000] + vnmsubfp128 v3, v4, v5, v3 + blr + #_ REGISTER_OUT v3 [C0E00000, C0E00000, C0E00000, C0E00000] + #_ REGISTER_OUT v4 [40400000, 40400000, 40400000, 40400000] + #_ REGISTER_OUT v5 [40400000, 40400000, 40400000, 40400000] diff --git a/src/xenia/cpu/ppc/testing/instr_vnor128.s b/src/xenia/cpu/ppc/testing/instr_vnor128.s new file mode 100644 index 000000000..b2d95ea39 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vnor128.s @@ -0,0 +1,8 @@ +test_vnor128_1: + #_ REGISTER_IN v3 [F0F0F0F0, 00000000, FFFFFFFF, 12345678] + #_ REGISTER_IN v4 [0F0F0F0F, FFFFFFFF, 00000000, ABCDEF01] + vnor128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [F0F0F0F0, 00000000, FFFFFFFF, 12345678] + #_ REGISTER_OUT v4 [0F0F0F0F, FFFFFFFF, 00000000, ABCDEF01] + #_ REGISTER_OUT v5 [F0F0F0F0, 00000000, FFFFFFFF, 12345678] diff --git a/src/xenia/cpu/ppc/testing/instr_vperm128.s b/src/xenia/cpu/ppc/testing/instr_vperm128.s new file mode 100644 index 000000000..fff7c93d9 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vperm128.s @@ -0,0 +1,21 @@ +test_vperm128_1: + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ REGISTER_IN v4 [11121314, 15161718, 191A1B1C, 1D1E1F20] + #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vperm128 v6, v3, v4, v2 + blr + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ REGISTER_OUT v4 [11121314, 15161718, 191A1B1C, 1D1E1F20] + #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] + #_ REGISTER_OUT v6 [01020304, 05060708, 090A0B0C, 0D0E0F10] + +test_vperm128_2: + #_ REGISTER_IN v3 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + #_ REGISTER_IN v4 [11111111, 22222222, 33333333, 44444444] + #_ REGISTER_IN v1 [10111213, 14151617, 18191A1B, 1C1D1E1F] + vperm128 v6, v3, v4, v1 + blr + #_ REGISTER_OUT v3 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + #_ REGISTER_OUT v4 [11111111, 22222222, 33333333, 44444444] + #_ REGISTER_OUT v1 [10111213, 14151617, 18191A1B, 1C1D1E1F] + #_ REGISTER_OUT v6 [11111111, 22222222, 33333333, 44444444] diff --git a/src/xenia/cpu/ppc/testing/instr_vrefp128.s b/src/xenia/cpu/ppc/testing/instr_vrefp128.s new file mode 100644 index 000000000..cfb68a60a --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrefp128.s @@ -0,0 +1,39 @@ +test_vrefp128_1: + # Reciprocal estimate: 1/[1.0, 2.0, 3.0, 4.0] ≈ [1.0, 0.5, 0.333, 0.25] + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + vrefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [3F800000, 3F000000, 3EAAAAAB, 3E800000] + +test_vrefp128_2: + # Reciprocal of larger values: 1/[5.0, 6.0, 7.0, 8.0] + #_ REGISTER_IN v4 [40A00000, 40C00000, 40E00000, 41000000] + vrefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [40A00000, 40C00000, 40E00000, 41000000] + #_ REGISTER_OUT v5 [3E4CCCCD, 3E2AAAAB, 3E124925, 3E000000] + +test_vrefp128_3: + # Reciprocal of fractions: 1/[0.5, 0.25, 0.125, 0.0625] + #_ REGISTER_IN v4 [3F000000, 3E800000, 3E000000, 3D800000] + vrefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F000000, 3E800000, 3E000000, 3D800000] + #_ REGISTER_OUT v5 [40000000, 40800000, 41000000, 41800000] + +test_vrefp128_4: + # Reciprocal of negative values: 1/[-1.0, -2.0, -3.0, -4.0] + #_ REGISTER_IN v4 [BF800000, C0000000, C0400000, C0800000] + vrefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [BF800000, C0000000, C0400000, C0800000] + #_ REGISTER_OUT v5 [BF800000, BF000000, BEAAAAAB, BE800000] + +test_vrefp128_5: + # Reciprocal of large values: 1/[100.0, 200.0, 300.0, 600.0] + #_ REGISTER_IN v4 [42C80000, 43480000, 43960000, 44160000] + vrefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [42C80000, 43480000, 43960000, 44160000] + #_ REGISTER_OUT v5 [3C23D70A, 3BA3D70A, 3B5A740E, 3ADA740E] diff --git a/src/xenia/cpu/ppc/testing/instr_vrfim128.s b/src/xenia/cpu/ppc/testing/instr_vrfim128.s new file mode 100644 index 000000000..74925d585 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrfim128.s @@ -0,0 +1,39 @@ +test_vrfim128_1: + # Floor positive numbers: [1.5, 2.25, 3.25, 4.5] -> [1.0, 2.0, 3.0, 4.0] + #_ REGISTER_IN v4 [3FC00000, 40100000, 40500000, 40900000] + vrfim128 v5, v4 + blr + #_ REGISTER_OUT v4 [3FC00000, 40100000, 40500000, 40900000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfim128_2: + # Floor negative numbers: [-1.5, -2.25, -3.25, -4.5] -> [-2.0, -3.0, -4.0, -5.0] + #_ REGISTER_IN v4 [BFC00000, C0100000, C0500000, C0900000] + vrfim128 v5, v4 + blr + #_ REGISTER_OUT v4 [BFC00000, C0100000, C0500000, C0900000] + #_ REGISTER_OUT v5 [C0000000, C0400000, C0800000, C0A00000] + +test_vrfim128_3: + # Floor integers (no change): [1.0, 2.0, 3.0, 4.0] + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + vrfim128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfim128_4: + # Floor zeros and small values: [0.0, -0.0, 0.5, -0.5] -> [0.0, -0.0, 0.0, -1.0] + #_ REGISTER_IN v4 [00000000, 80000000, 3F000000, BF000000] + vrfim128 v5, v4 + blr + #_ REGISTER_OUT v4 [00000000, 80000000, 3F000000, BF000000] + #_ REGISTER_OUT v5 [00000000, 80000000, 00000000, BF800000] + +test_vrfim128_5: + # Floor fractional values: [0.75, 0.9, 1.0, 1.1] -> [0.0, 0.0, 1.0, 1.0] + #_ REGISTER_IN v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD] + vrfim128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F400000, 3F666666, 3F800000, 3F8CCCCD] + #_ REGISTER_OUT v5 [00000000, 00000000, 3F800000, 3F800000] diff --git a/src/xenia/cpu/ppc/testing/instr_vrfin128.s b/src/xenia/cpu/ppc/testing/instr_vrfin128.s new file mode 100644 index 000000000..544758773 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrfin128.s @@ -0,0 +1,39 @@ +test_vrfin128_1: + # Round to nearest: [1.4, 1.5, 1.6, 2.5] -> [1.0, 2.0, 2.0, 2.0] + #_ REGISTER_IN v4 [3FB33333, 3FC00000, 3FCCCCCD, 40200000] + vrfin128 v5, v4 + blr + #_ REGISTER_OUT v4 [3FB33333, 3FC00000, 3FCCCCCD, 40200000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40000000, 40000000] + +test_vrfin128_2: + # Round negative to nearest: [-1.4, -1.5, -1.6, -2.5] -> [-1.0, -2.0, -2.0, -2.0] + #_ REGISTER_IN v4 [BFB33333, BFC00000, BFCCCCCD, C0200000] + vrfin128 v5, v4 + blr + #_ REGISTER_OUT v4 [BFB33333, BFC00000, BFCCCCCD, C0200000] + #_ REGISTER_OUT v5 [BF800000, C0000000, C0000000, C0000000] + +test_vrfin128_3: + # Round integers (no change): [1.0, 2.0, 3.0, 4.0] + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + vrfin128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfin128_4: + # Round zeros and 0.5: [0.0, -0.0, 0.5, -0.5] -> [0.0, -0.0, 0.0, -0.0] + #_ REGISTER_IN v4 [00000000, 80000000, 3F000000, BF000000] + vrfin128 v5, v4 + blr + #_ REGISTER_OUT v4 [00000000, 80000000, 3F000000, BF000000] + #_ REGISTER_OUT v5 [00000000, 80000000, 00000000, 80000000] + +test_vrfin128_5: + # Round small values: [0.1, 0.4, 0.6, 0.9] -> [0.0, 0.0, 1.0, 1.0] + #_ REGISTER_IN v4 [3DCCCCCD, 3ECCCCCD, 3F19999A, 3F666666] + vrfin128 v5, v4 + blr + #_ REGISTER_OUT v4 [3DCCCCCD, 3ECCCCCD, 3F19999A, 3F666666] + #_ REGISTER_OUT v5 [00000000, 00000000, 3F800000, 3F800000] diff --git a/src/xenia/cpu/ppc/testing/instr_vrfip128.s b/src/xenia/cpu/ppc/testing/instr_vrfip128.s new file mode 100644 index 000000000..e297cd524 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrfip128.s @@ -0,0 +1,39 @@ +test_vrfip128_1: + # Ceiling positive numbers: [1.1, 1.5, 2.9, 3.1] -> [2.0, 2.0, 3.0, 4.0] + #_ REGISTER_IN v4 [3F8CCCCD, 3FC00000, 403CCCCD, 40466666] + vrfip128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F8CCCCD, 3FC00000, 403CCCCD, 40466666] + #_ REGISTER_OUT v5 [40000000, 40000000, 40400000, 40800000] + +test_vrfip128_2: + # Ceiling negative numbers: [-1.1, -1.5, -2.9, -3.1] -> [-1.0, -1.0, -2.0, -3.0] + #_ REGISTER_IN v4 [BF8CCCCD, BFC00000, C03CCCCD, C0466666] + vrfip128 v5, v4 + blr + #_ REGISTER_OUT v4 [BF8CCCCD, BFC00000, C03CCCCD, C0466666] + #_ REGISTER_OUT v5 [BF800000, BF800000, C0000000, C0400000] + +test_vrfip128_3: + # Ceiling integers (no change): [1.0, 2.0, 3.0, 4.0] + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + vrfip128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfip128_4: + # Ceiling zeros and small values: [0.0, -0.0, 0.1, -0.1] -> [0.0, -0.0, 1.0, -0.0] + #_ REGISTER_IN v4 [00000000, 80000000, 3DCCCCCD, BDCCCCCD] + vrfip128 v5, v4 + blr + #_ REGISTER_OUT v4 [00000000, 80000000, 3DCCCCCD, BDCCCCCD] + #_ REGISTER_OUT v5 [00000000, 80000000, 3F800000, 80000000] + +test_vrfip128_5: + # Ceiling fractional values: [0.01, 0.99, 1.0, 1.01] -> [1.0, 1.0, 1.0, 2.0] + #_ REGISTER_IN v4 [3C23D70A, 3F7D70A4, 3F800000, 3F828F5C] + vrfip128 v5, v4 + blr + #_ REGISTER_OUT v4 [3C23D70A, 3F7D70A4, 3F800000, 3F828F5C] + #_ REGISTER_OUT v5 [3F800000, 3F800000, 3F800000, 40000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vrfiz128.s b/src/xenia/cpu/ppc/testing/instr_vrfiz128.s new file mode 100644 index 000000000..7b31a1bcd --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrfiz128.s @@ -0,0 +1,39 @@ +test_vrfiz128_1: + # Truncate positive numbers: [1.1, 1.9, 2.5, 3.9] -> [1.0, 1.0, 2.0, 3.0] + #_ REGISTER_IN v4 [3F8CCCCD, 3FF33333, 40200000, 4079999A] + vrfiz128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F8CCCCD, 3FF33333, 40200000, 4079999A] + #_ REGISTER_OUT v5 [3F800000, 3F800000, 40000000, 40400000] + +test_vrfiz128_2: + # Truncate negative numbers: [-1.1, -1.9, -2.5, -3.9] -> [-1.0, -1.0, -2.0, -3.0] + #_ REGISTER_IN v4 [BF8CCCCD, BFF33333, C0200000, C079999A] + vrfiz128 v5, v4 + blr + #_ REGISTER_OUT v4 [BF8CCCCD, BFF33333, C0200000, C079999A] + #_ REGISTER_OUT v5 [BF800000, BF800000, C0000000, C0400000] + +test_vrfiz128_3: + # Truncate integers (no change): [1.0, 2.0, 3.0, 4.0] + #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000] + vrfiz128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000] + #_ REGISTER_OUT v5 [3F800000, 40000000, 40400000, 40800000] + +test_vrfiz128_4: + # Truncate zeros and small values: [0.0, -0.0, 0.9, -0.9] -> [0.0, -0.0, 0.0, -0.0] + #_ REGISTER_IN v4 [00000000, 80000000, 3F666666, BF666666] + vrfiz128 v5, v4 + blr + #_ REGISTER_OUT v4 [00000000, 80000000, 3F666666, BF666666] + #_ REGISTER_OUT v5 [00000000, 80000000, 00000000, 80000000] + +test_vrfiz128_5: + # Truncate mixed values: [0.1, 0.5, 1.5, 2.9] -> [0.0, 0.0, 1.0, 2.0] + #_ REGISTER_IN v4 [3DCCCCCD, 3F000000, 3FC00000, 403CCCCD] + vrfiz128 v5, v4 + blr + #_ REGISTER_OUT v4 [3DCCCCCD, 3F000000, 3FC00000, 403CCCCD] + #_ REGISTER_OUT v5 [00000000, 00000000, 3F800000, 40000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vrlw128.s b/src/xenia/cpu/ppc/testing/instr_vrlw128.s new file mode 100644 index 000000000..8eeb0a355 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrlw128.s @@ -0,0 +1,8 @@ +test_vrlw128_1: + #_ REGISTER_IN v3 [80000000, 00000001, 12345678, FFFFFFFF] + #_ REGISTER_IN v4 [00000001, 00000008, 00000004, 00000010] + vrlw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [80000000, 00000001, 12345678, FFFFFFFF] + #_ REGISTER_OUT v4 [00000001, 00000008, 00000004, 00000010] + #_ REGISTER_OUT v5 [00000001, 00000100, 23456781, FFFFFFFF] diff --git a/src/xenia/cpu/ppc/testing/instr_vrsqrtefp128.s b/src/xenia/cpu/ppc/testing/instr_vrsqrtefp128.s new file mode 100644 index 000000000..a0bb89490 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vrsqrtefp128.s @@ -0,0 +1,39 @@ +test_vrsqrtefp128_1: + # Reciprocal square root: 1/sqrt([1.0, 4.0, 9.0, 16.0]) ≈ [1.0, 0.5, 0.333, 0.25] + #_ REGISTER_IN v4 [3F800000, 40800000, 41100000, 41800000] + vrsqrtefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 40800000, 41100000, 41800000] + #_ REGISTER_OUT v5 [3F7FF400, 3EFFF400, 3EAAA500, 3E7FF400] + +test_vrsqrtefp128_2: + # Reciprocal square root of larger values + #_ REGISTER_IN v4 [41C80000, 42480000, 42C80000, 43480000] + vrsqrtefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [41C80000, 42480000, 42C80000, 43480000] + #_ REGISTER_OUT v5 [3E4CCA00, 3E10CE00, 3DCCCA00, 3D90CE00] + +test_vrsqrtefp128_3: + # Reciprocal square root of fractions + #_ REGISTER_IN v4 [3F000000, 3E800000, 3E000000, 3D800000] + vrsqrtefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F000000, 3E800000, 3E000000, 3D800000] + #_ REGISTER_OUT v5 [3FB4FD00, 3FFFF400, 4034FD00, 407FF400] + +test_vrsqrtefp128_4: + # Reciprocal square root of unity variations + #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000] + vrsqrtefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000] + #_ REGISTER_OUT v5 [3F7FF400, 3F7FF400, 3F7FF400, 3F7FF400] + +test_vrsqrtefp128_5: + # Reciprocal square root of very small values + #_ REGISTER_IN v4 [3C23D70A, 3BA3D70A, 3B23D70A, 3AA3D70A] + vrsqrtefp128 v5, v4 + blr + #_ REGISTER_OUT v4 [3C23D70A, 3BA3D70A, 3B23D70A, 3AA3D70A] + #_ REGISTER_OUT v5 [412004FD, 41624CF5, 41A004FD, 41E24CF5] diff --git a/src/xenia/cpu/ppc/testing/instr_vsel128.s b/src/xenia/cpu/ppc/testing/instr_vsel128.s new file mode 100644 index 000000000..b59886ed3 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vsel128.s @@ -0,0 +1,10 @@ +test_vsel128_1: + #_ REGISTER_IN v2 [FFFFFFFF, 00000000, FFFFFFFF, 00000000] + #_ REGISTER_IN v3 [11111111, 22222222, 33333333, 44444444] + #_ REGISTER_IN v4 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + vsel128 v6, v3, v4, v2 + blr + #_ REGISTER_OUT v2 [FFFFFFFF, 00000000, FFFFFFFF, 00000000] + #_ REGISTER_OUT v3 [11111111, 22222222, 33333333, 44444444] + #_ REGISTER_OUT v4 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + #_ REGISTER_OUT v6 [AAAAAAAA, 22222222, CCCCCCCC, 44444444] diff --git a/src/xenia/cpu/ppc/testing/instr_vsldoi128.s b/src/xenia/cpu/ppc/testing/instr_vsldoi128.s new file mode 100644 index 000000000..94e30e183 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vsldoi128.s @@ -0,0 +1,8 @@ +test_vsldoi128_1: + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ REGISTER_IN v4 [11121314, 15161718, 191A1B1C, 1D1E1F20] + vsldoi128 v5, v3, v4, 4 + blr + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ REGISTER_OUT v4 [11121314, 15161718, 191A1B1C, 1D1E1F20] + #_ REGISTER_OUT v5 [05060708, 090A0B0C, 0D0E0F10, 11121314] diff --git a/src/xenia/cpu/ppc/testing/instr_vslo128.s b/src/xenia/cpu/ppc/testing/instr_vslo128.s new file mode 100644 index 000000000..7ee4674f7 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vslo128.s @@ -0,0 +1,8 @@ +test_vslo128_1: + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ REGISTER_IN v4 [00000008, 00000000, 00000000, 00000000] + vslo128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ REGISTER_OUT v4 [00000008, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [01020304, 05060708, 090A0B0C, 0D0E0F10] diff --git a/src/xenia/cpu/ppc/testing/instr_vslw128.s b/src/xenia/cpu/ppc/testing/instr_vslw128.s new file mode 100644 index 000000000..06eb155bd --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vslw128.s @@ -0,0 +1,8 @@ +test_vslw128_1: + #_ REGISTER_IN v3 [00000001, 00000002, 00000004, 00000008] + #_ REGISTER_IN v4 [00000001, 00000002, 00000003, 00000004] + vslw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [00000001, 00000002, 00000004, 00000008] + #_ REGISTER_OUT v4 [00000001, 00000002, 00000003, 00000004] + #_ REGISTER_OUT v5 [00000002, 00000008, 00000020, 00000080] diff --git a/src/xenia/cpu/ppc/testing/instr_vspltisw128.s b/src/xenia/cpu/ppc/testing/instr_vspltisw128.s new file mode 100644 index 000000000..4b4bea9b2 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vspltisw128.s @@ -0,0 +1,11 @@ +test_vspltisw128_1: + #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] + vspltisw128 v3, 5 + blr + #_ REGISTER_OUT v3 [00000005, 00000005, 00000005, 00000005] + +test_vspltisw128_2: + #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] + vspltisw128 v4, -16 + blr + #_ REGISTER_OUT v4 [FFFFFFF0, FFFFFFF0, FFFFFFF0, FFFFFFF0] diff --git a/src/xenia/cpu/ppc/testing/instr_vspltw128.s b/src/xenia/cpu/ppc/testing/instr_vspltw128.s new file mode 100644 index 000000000..09aa5ff51 --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vspltw128.s @@ -0,0 +1,13 @@ +test_vspltw128_1: + #_ REGISTER_IN v3 [11111111, 22222222, 33333333, 44444444] + vspltw128 v4, v3, 0 + blr + #_ REGISTER_OUT v3 [11111111, 22222222, 33333333, 44444444] + #_ REGISTER_OUT v4 [11111111, 11111111, 11111111, 11111111] + +test_vspltw128_2: + #_ REGISTER_IN v3 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + vspltw128 v4, v3, 2 + blr + #_ REGISTER_OUT v3 [AAAAAAAA, BBBBBBBB, CCCCCCCC, DDDDDDDD] + #_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC] diff --git a/src/xenia/cpu/ppc/testing/instr_vsraw128.s b/src/xenia/cpu/ppc/testing/instr_vsraw128.s new file mode 100644 index 000000000..1503559ac --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vsraw128.s @@ -0,0 +1,8 @@ +test_vsraw128_1: + #_ REGISTER_IN v3 [80000000, 00000100, FFFFFFF0, 00000008] + #_ REGISTER_IN v4 [00000001, 00000002, 00000003, 00000004] + vsraw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [80000000, 00000100, FFFFFFF0, 00000008] + #_ REGISTER_OUT v4 [00000001, 00000002, 00000003, 00000004] + #_ REGISTER_OUT v5 [C0000000, 00000040, FFFFFFFE, 00000000] diff --git a/src/xenia/cpu/ppc/testing/instr_vsro128.s b/src/xenia/cpu/ppc/testing/instr_vsro128.s new file mode 100644 index 000000000..93f966bea --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vsro128.s @@ -0,0 +1,8 @@ +test_vsro128_1: + #_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ REGISTER_IN v4 [00000008, 00000000, 00000000, 00000000] + vsro128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10] + #_ REGISTER_OUT v4 [00000008, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v5 [01020304, 05060708, 090A0B0C, 0D0E0F10] diff --git a/src/xenia/cpu/ppc/testing/instr_vsrw128.s b/src/xenia/cpu/ppc/testing/instr_vsrw128.s new file mode 100644 index 000000000..e0500e6bf --- /dev/null +++ b/src/xenia/cpu/ppc/testing/instr_vsrw128.s @@ -0,0 +1,8 @@ +test_vsrw128_1: + #_ REGISTER_IN v3 [80000000, 00000100, 00000020, 00000008] + #_ REGISTER_IN v4 [00000001, 00000002, 00000003, 00000004] + vsrw128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [80000000, 00000100, 00000020, 00000008] + #_ REGISTER_OUT v4 [00000001, 00000002, 00000003, 00000004] + #_ REGISTER_OUT v5 [40000000, 00000040, 00000004, 00000000]