Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental

src/xenia/gpu/texture_util.h

@@ -144,24 +144,27 @@ struct TextureGuestLayout {
     // multiplied by the array slice count.
     uint32_t array_slice_stride_bytes;
 
-    // Estimated amount of memory this level occupies, and variables involved in
-    // its calculation. Not aligned to kTextureSubresourceAlignmentBytes. For
-    // tiled textures, this will be rounded to 32x32x4 blocks (or 32x32x1
-    // depending on the dimension), but for the linear subresources, this may be
-    // significantly (including less 4 KB pages) smaller than the aligned size
-    // (like for 4E4D083E where aligning the height of a 1280x720 linear texture
-    // results in access violations). For the linear mip tail, this includes all
-    // the mip levels stored in it. If the width is bigger than the pitch, this
-    // will also be taken into account for the last row so all memory actually
-    // used by the texture will be loaded, and may be bigger than the distance
-    // between array slices or levels. The purpose of this parameter is to make
-    // the memory amount that needs to be resident as close to the real amount
-    // as possible, to make sure all the needed data will be read, but also, if
-    // possible, unneeded memory pages won't be accessed (since that may trigger
-    // an access violation on the CPU).
+    // The exclusive upper bound of blocks needed at this level (this level for
+    // non-packed levels, or all the packed levels for the packed mip tail).
     uint32_t x_extent_blocks;
     uint32_t y_extent_blocks;
     uint32_t z_extent;
+    // Estimated amount of memory this level occupies. Not aligned to
+    // kTextureSubresourceAlignmentBytes. For tiled textures, this will be
+    // calculated for the extent rounded to 32x32x4 blocks (or 32x32x1 depending
+    // on the dimensionality), but for linear textures, as well as for mips of
+    // non-power-of-two tiled textures, this may be significantly (including
+    // less 4 KB pages) smaller than the aligned size (like for 4E4D083E where
+    // aligning the height of a 1280x720 linear texture results in access
+    // violations). For the linear mip tail, this includes all the mip levels
+    // stored in it. If the width is bigger than the pitch, this will also be
+    // taken into account for the last row so all memory actually used by the
+    // texture will be loaded, and may be bigger than the distance between array
+    // slices or levels. The purpose of this parameter is to make the memory
+    // amount that needs to be resident as close to the real amount as possible,
+    // to make sure all the needed data will be read, but also, if possible,
+    // unneeded memory pages won't be accessed (since that may trigger an access
+    // violation on the CPU).
     uint32_t array_slice_data_extent_bytes;
     // Including all array slices.
     uint32_t level_data_extent_bytes;