From 2bb7c8dbf5e10346c44564f41aaa6f4b5722815e Mon Sep 17 00:00:00 2001 From: "Herman S." <429230+has207@users.noreply.github.com> Date: Sun, 19 Oct 2025 15:13:57 +0900 Subject: [PATCH] [Testing] Fix tests to use opcode mnemonics --- src/xenia/cpu/ppc/testing/instr_lvx128.s | 28 ++---- src/xenia/cpu/ppc/testing/instr_vpermwi128.s | 12 +-- src/xenia/cpu/ppc/testing/instr_vpkd3d128.s | 93 +++++++------------ src/xenia/cpu/ppc/testing/instr_vpkuhum128.s | 70 +++++++------- src/xenia/cpu/ppc/testing/instr_vupkd3d128.s | 55 +++++------ .../binutils/binutils-2.24-vmx128.patch | 6 +- 6 files changed, 102 insertions(+), 162 deletions(-) diff --git a/src/xenia/cpu/ppc/testing/instr_lvx128.s b/src/xenia/cpu/ppc/testing/instr_lvx128.s index 695dc324e..61ab472d2 100644 --- a/src/xenia/cpu/ppc/testing/instr_lvx128.s +++ b/src/xenia/cpu/ppc/testing/instr_lvx128.s @@ -3,8 +3,7 @@ test_lvx128_1: #_ MEMORY_IN 0x0000000010001000 [01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10] #_ REGISTER_IN r4 0x0000000010001000 li r5, 0 - # lvx128 v3, r4, r5 - .long 0x106428C3 # lvx128 v3, r4, r5 + lvx128 v3, r4, r5 blr #_ REGISTER_OUT r4 0x0000000010001000 #_ REGISTER_OUT r5 0 @@ -16,8 +15,7 @@ test_lvx128_2: #_ MEMORY_IN 0x0000000010001010 [AA, BB, CC, DD, EE, FF, 00, 11, 22, 33, 44, 55, 66, 77, 88, 99] #_ REGISTER_IN r4 0x0000000010001000 li r5, 16 - # lvx128 v3, r4, r5 - .long 0x106428C3 + lvx128 v3, r4, r5 blr #_ REGISTER_OUT r4 0x0000000010001000 #_ REGISTER_OUT r5 16 @@ -28,8 +26,7 @@ test_lvx128_3: #_ MEMORY_IN 0x0000000010001000 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, FA, FB, FC, FD, FE, FF] #_ REGISTER_IN r4 0x0000000010001000 li r5, 13 # unaligned - # lvx128 v3, r4, r5 - .long 0x106428C3 + lvx128 v3, r4, r5 blr #_ REGISTER_OUT r4 0x0000000010001000 #_ REGISTER_OUT r5 13 @@ -43,8 +40,7 @@ test_lvx128_4: #_ MEMORY_IN 0x0000000010001020 [DE, AD, BE, EF, CA, FE, BA, BE, 00, 11, 22, 33, 44, 55, 66, 77] #_ REGISTER_IN r4 0x0000000010001000 li r5, 32 - # lvx128 v3, r4, r5 - .long 0x106428C3 + lvx128 v3, r4, r5 blr #_ REGISTER_OUT r4 0x0000000010001000 #_ REGISTER_OUT r5 32 @@ -55,8 +51,7 @@ test_lvx128_5: #_ MEMORY_IN 0x0000000010001000 [00, 11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF] #_ REGISTER_IN r4 0x0000000010001000 li r5, 0 - # lvx128 v3, r4, r5 - .long 0x106428C3 + lvx128 v3, r4, r5 blr #_ REGISTER_OUT r4 0x0000000010001000 #_ REGISTER_OUT r5 0 @@ -67,8 +62,8 @@ test_lvx128_6: #_ MEMORY_IN 0x0000000010001000 [A5, A5, A5, A5, 5A, 5A, 5A, 5A, FF, 00, FF, 00, 00, FF, 00, FF] #_ REGISTER_IN r4 0x0000000010001000 li r5, 0 - # lvx128 v100, r4, r5 - .long 0x1C8428C3 # lvx128 v100, r4, r5 + # lvx128 v100, r4, r5 (binutils doesn't support high register names) + .long 0x1C8428C3 blr #_ REGISTER_OUT r5 0 #_ REGISTER_OUT v100 [00000000, 00000000, 00000000, 00000000] @@ -80,14 +75,11 @@ test_lvx128_7: #_ MEMORY_IN 0x0000000010001020 [99, 99, 99, 99, AA, AA, AA, AA, BB, BB, BB, BB, CC, CC, CC, CC] #_ REGISTER_IN r4 0x0000000010001000 li r5, 0 - # lvx128 v3, r4, r5 - .long 0x106428C3 + lvx128 v3, r4, r5 li r5, 16 - # lvx128 v4, r4, r5 - .long 0x108428C3 + lvx128 v4, r4, r5 li r5, 32 - # lvx128 v5, r4, r5 - .long 0x10A428C3 + lvx128 v5, r4, r5 blr #_ REGISTER_OUT r4 0x0000000010001000 #_ REGISTER_OUT r5 32 diff --git a/src/xenia/cpu/ppc/testing/instr_vpermwi128.s b/src/xenia/cpu/ppc/testing/instr_vpermwi128.s index 158a0e608..0c42d27f9 100644 --- a/src/xenia/cpu/ppc/testing/instr_vpermwi128.s +++ b/src/xenia/cpu/ppc/testing/instr_vpermwi128.s @@ -1,8 +1,7 @@ test_vpermwi128_1: #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] # to 0,1,2,3 - # vpermwi128 v4, v3, 0x1B - .long 0x189B1A10 + vpermwi128 v4, v3, 0x1B blr #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] @@ -10,8 +9,7 @@ test_vpermwi128_1: test_vpermwi128_2: #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] # to 3,2,1,0 - # vpermwi128 v4, v3, 0xE4 - .long 0x18841BD0 + vpermwi128 v4, v3, 0xE4 blr #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v4 [0C0D0E0F, 08090A0B, 04050607, 00010203] @@ -19,8 +17,7 @@ test_vpermwi128_2: test_vpermwi128_3: #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] # to 0,0,0,0 - # vpermwi128 v4, v3, 0 - .long 0x18801A10 + vpermwi128 v4, v3, 0 blr #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v4 [00010203, 00010203, 00010203, 00010203] @@ -28,8 +25,7 @@ test_vpermwi128_3: test_vpermwi128_4: #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] # to 3,3,3,3 - # vpermwi128 v4, v3, 0xFF - .long 0x189F1BD0 + vpermwi128 v4, v3, 0xFF blr #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v4 [0C0D0E0F, 0C0D0E0F, 0C0D0E0F, 0C0D0E0F] diff --git a/src/xenia/cpu/ppc/testing/instr_vpkd3d128.s b/src/xenia/cpu/ppc/testing/instr_vpkd3d128.s index e4acd59f2..39e2922db 100644 --- a/src/xenia/cpu/ppc/testing/instr_vpkd3d128.s +++ b/src/xenia/cpu/ppc/testing/instr_vpkd3d128.s @@ -10,37 +10,31 @@ # must not be zero # 1 = 00000000 00000000 00000000 FFFFFFFF # 2 = 00000000 00000000 FFFFFFFF FFFFFFFF -# 3 = same as 2? except mask3/shift3 +# 3 = 00000000 00000000 00000000 FFFFFFFF (special case) # shift: # 0 = no shift # 1 = shift left by one word -# 2 ... -# 3 ... -# special case: mask3/shift3 = 00000000 00000000 00000000 FFFFFFFF - -# vpkd3d128 is broken in binutils, so these are hand coded +# 2 = shift left by two words +# 3 = shift left by three words test_vpkd3d128_d3dcolor_invalid_0: #_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 1, 0 - .long 0x18811E10 + vpkd3d128 v4, v3, 0, 1, 0 blr #_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vpkd3d128_d3dcolor_invalid_1: #_ REGISTER_IN v3 [40800000, 40000000, C2F60000, 4B3BDF83] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 1, 0 - .long 0x18811E10 + vpkd3d128 v4, v3, 0, 1, 0 blr #_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, 4B3BDF83] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF0000] test_vpkd3d128_d3dcolor_invalid_2: #_ REGISTER_IN v3 [40800000, 40000000, C2F60000, FFFFFFFF] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 1, 0 - .long 0x18811E10 + vpkd3d128 v4, v3, 0, 1, 0 blr #_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, FFFFFFFF] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00FF0000] @@ -48,32 +42,28 @@ test_vpkd3d128_d3dcolor_invalid_2: test_vpkd3d128_d3dcolor_1_0: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 1, 0 - .long 0x18811E10 + vpkd3d128 v4, v3, 0, 1, 0 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vpkd3d128_d3dcolor_1_1: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 1, 1 - .long 0x18811E50 + vpkd3d128 v4, v3, 0, 1, 1 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 04010203, CDCDCDCD] test_vpkd3d128_d3dcolor_1_2: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 1, 2 - .long 0x18811E90 + vpkd3d128 v4, v3, 0, 1, 2 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [CDCDCDCD, 04010203, CDCDCDCD, CDCDCDCD] test_vpkd3d128_d3dcolor_1_3: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 1, 3 - .long 0x18811ED0 + vpkd3d128 v4, v3, 0, 1, 3 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD] @@ -81,32 +71,28 @@ test_vpkd3d128_d3dcolor_1_3: test_vpkd3d128_d3dcolor_2_0: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 2, 0 - .long 0x18821E10 + vpkd3d128 v4, v3, 0, 2, 0 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203] test_vpkd3d128_d3dcolor_2_1: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 2, 1 - .long 0x18821E50 + vpkd3d128 v4, v3, 0, 2, 1 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD] test_vpkd3d128_d3dcolor_2_2: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 2, 2 - .long 0x18821E90 + vpkd3d128 v4, v3, 0, 2, 2 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD] test_vpkd3d128_d3dcolor_2_3: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 2, 3 - .long 0x18821ED0 + vpkd3d128 v4, v3, 0, 2, 3 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD] @@ -114,32 +100,28 @@ test_vpkd3d128_d3dcolor_2_3: test_vpkd3d128_d3dcolor_3_0: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 3, 0 - .long 0x18831E10 + vpkd3d128 v4, v3, 0, 3, 0 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203] test_vpkd3d128_d3dcolor_3_1: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 3, 1 - .long 0x18831E50 + vpkd3d128 v4, v3, 0, 3, 1 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD] test_vpkd3d128_d3dcolor_3_2: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 3, 2 - .long 0x18831E90 + vpkd3d128 v4, v3, 0, 3, 2 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD] test_vpkd3d128_d3dcolor_3_3: #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 0, 3, 3 - .long 0x18831ED0 + vpkd3d128 v4, v3, 0, 3, 3 blr #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] @@ -148,16 +130,14 @@ test_vpkd3d128_d3dcolor_3_3: test_vpkd3d128_short2_invalid_0: #_ REGISTER_IN v3 [43817E00, C37CFC00, 42A23EC8, 403DB757] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 1, 1, 0 - .long 0x18851E10 + vpkd3d128 v4, v3, 1, 1, 0 blr #_ REGISTER_OUT v3 [43817E00, C37CFC00, 42A23EC8, 403DB757] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001] test_vpkd3d128_short2_invalid_1: #_ REGISTER_IN v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 1, 1, 0 - .long 0x18851E10 + vpkd3d128 v4, v3, 1, 1, 0 blr #_ REGISTER_OUT v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001] @@ -165,24 +145,21 @@ test_vpkd3d128_short2_invalid_1: test_vpkd3d128_short2_0: #_ REGISTER_IN v3 [40407FFF, 403F8001, 00000000, 00000000] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 1, 1, 0 - .long 0x18851E10 + vpkd3d128 v4, v3, 1, 1, 0 blr #_ REGISTER_OUT v3 [40407FFF, 403F8001, 00000000, 00000000] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001] test_vpkd3d128_short2_1: #_ REGISTER_IN v3 [40404000, 403FC000, 40400003, 403F8001] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 1, 1, 0 - .long 0x18851E10 + vpkd3d128 v4, v3, 1, 1, 0 blr #_ REGISTER_OUT v3 [40404000, 403FC000, 40400003, 403F8001] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 4000C000] test_vpkd3d128_short2_2: #_ REGISTER_IN v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 1, 1, 0 - .long 0x18851E10 + vpkd3d128 v4, v3, 1, 1, 0 blr #_ REGISTER_OUT v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFFF333] @@ -191,8 +168,7 @@ test_vpkd3d128_short4_0: # v3 = [1.5, -1.5, 1.5, -1.5] #_ REGISTER_IN v3 [403F8001, 403FFFF8, 4040007F, 40400000] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 4, 2, 0 - .long 0x18921E10 + vpkd3d128 v4, v3, 4, 2, 0 blr #_ REGISTER_OUT v3 [403F8001, 403FFFF8, 4040007F, 40400000] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 8001FFF8, 007F0000] @@ -200,24 +176,21 @@ test_vpkd3d128_short4_0: test_vpkd3d128_uint_2101010_0: #_ REGISTER_IN v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 2, 1, 0 - .long 0x18891E10 + vpkd3d128 v4, v3, 2, 1, 0 blr #_ REGISTER_OUT v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, E0180601] test_vpkd3d128_uint_2101010_1: #_ REGISTER_IN v3 [42C80000, C2C80000, 40400000, 3F800000] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 2, 1, 0 - .long 0x18891E10 + vpkd3d128 v4, v3, 2, 1, 0 blr #_ REGISTER_OUT v3 [42C80000, C2C80000, 40400000, 3F800000] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 000805FF] test_vpkd3d128_uint_2101010_2: #_ REGISTER_IN v3 [3F000000, BF000000, 3F800000, 00000000] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 2, 1, 0 - .long 0x18891E10 + vpkd3d128 v4, v3, 2, 1, 0 blr #_ REGISTER_OUT v3 [3F000000, BF000000, 3F800000, 00000000] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 20180601] @@ -226,16 +199,14 @@ test_vpkd3d128_uint_2101010_2: test_vpkd3d128_float16_2_invalid_0: #_ REGISTER_IN v3 [3FC00000, BFC00000, 42A23EC8, 403DB757] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 3, 1, 0 - .long 0x188D1E10 + vpkd3d128 v4, v3, 3, 1, 0 blr #_ REGISTER_OUT v3 [3FC00000, BFC00000, 42A23EC8, 403DB757] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3E00BE00] test_vpkd3d128_float16_2_0: #_ REGISTER_IN v3 [3F000000, BF000000, 00000000, 00000000] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 3, 1, 0 - .long 0x188D1E10 + vpkd3d128 v4, v3, 3, 1, 0 blr #_ REGISTER_OUT v3 [3F000000, BF000000, 00000000, 00000000] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3800B800] @@ -243,16 +214,14 @@ test_vpkd3d128_float16_2_0: test_vpkd3d128_float16_4_invalid_0: #_ REGISTER_IN v3 [3FC00000, BFC00000, 3FC00000, BFC00000] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 5, 2, 0 - .long 0x18961E10 + vpkd3d128 v4, v3, 5, 2, 0 blr #_ REGISTER_OUT v3 [3FC00000, BFC00000, 3FC00000, BFC00000] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3E00BE00, 3E00BE00] test_vpkd3d128_float16_4_0: #_ REGISTER_IN v3 [3F000000, BF000000, 3F800000, BF800000] #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] - # vpkd3d128 v4, v3, 5, 2, 0 - .long 0x18961E10 + vpkd3d128 v4, v3, 5, 2, 0 blr #_ REGISTER_OUT v3 [3F000000, BF000000, 3F800000, BF800000] #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3800B800, 3C00BC00] diff --git a/src/xenia/cpu/ppc/testing/instr_vpkuhum128.s b/src/xenia/cpu/ppc/testing/instr_vpkuhum128.s index 2834ede78..db4221743 100644 --- a/src/xenia/cpu/ppc/testing/instr_vpkuhum128.s +++ b/src/xenia/cpu/ppc/testing/instr_vpkuhum128.s @@ -1,39 +1,35 @@ -#vpkuhum128 isn't implemented yet -#test_vpkuhum128_1: -# # {0, 1, 2, 3, 4, 5, 6, 7} -# #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007] -# # {8, 9, 10, 11, 12, 13, 14, 15} -# #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F] -# vpkuhum128 v5, v3, v4 -# blr -# #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007] -# #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F] -# # {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} -# #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F] -# blr +test_vpkuhum128_1: + # {0, 1, 2, 3, 4, 5, 6, 7} + #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007] + # {8, 9, 10, 11, 12, 13, 14, 15} + #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F] + vpkuhum128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007] + #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F] + # {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} + #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F] -#test_vpkuhum128_2: -# # {-8, -7, -6, -5, -4, -3, -2, -1} -# #_ REGISTER_IN v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF] -# # {0, 1, 2, 3, 4, 5, 6, 7} -# #_ REGISTER_IN v4 [00000001, 00020003, 00040005, 00060007] -# vpkuhum128 v5, v3, v4 -# blr -# #_ REGISTER_OUT v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF] -# #_ REGISTER_OUT v4 [00000001, 00020003, 00040005, 00060007] -# # {-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7} -# #_ REGISTER_OUT v5 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] -# blr +test_vpkuhum128_2: + # {-8, -7, -6, -5, -4, -3, -2, -1} + #_ REGISTER_IN v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF] + # {0, 1, 2, 3, 4, 5, 6, 7} + #_ REGISTER_IN v4 [00000001, 00020003, 00040005, 00060007] + vpkuhum128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF] + #_ REGISTER_OUT v4 [00000001, 00020003, 00040005, 00060007] + # {-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7} + #_ REGISTER_OUT v5 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] -#test_vpkuhum128_3: -# # {0, 65535, 65535, 0, 0, 0, 65535, 0} -# #_ REGISTER_IN v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] -# # {65535, 0, 0, 65535, 65535, 65535, 0, 65535} -# #_ REGISTER_IN v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF] -# vpkuhum128 v5, v3, v4 -# blr -# #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] -# #_ REGISTER_OUT v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF] -# # {0, 255, 255, 0, 0, 0, 255, 0, 255, 0, 0, 255, 255, 255, 0, 255} -# #_ REGISTER_OUT v5 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] -# blr +test_vpkuhum128_3: + # {0, 65535, 65535, 0, 0, 0, 65535, 0} + #_ REGISTER_IN v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] + # {65535, 0, 0, 65535, 65535, 65535, 0, 65535} + #_ REGISTER_IN v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF] + vpkuhum128 v5, v3, v4 + blr + #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] + #_ REGISTER_OUT v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF] + # {0, 255, 255, 0, 0, 0, 255, 0, 255, 0, 0, 255, 255, 255, 0, 255} + #_ REGISTER_OUT v5 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] diff --git a/src/xenia/cpu/ppc/testing/instr_vupkd3d128.s b/src/xenia/cpu/ppc/testing/instr_vupkd3d128.s index b16b299d4..ad4290f6f 100644 --- a/src/xenia/cpu/ppc/testing/instr_vupkd3d128.s +++ b/src/xenia/cpu/ppc/testing/instr_vupkd3d128.s @@ -5,76 +5,63 @@ # 3 = PACK_TYPE_FLOAT16_2 # 5 = PACK_TYPE_FLOAT16_4 -# vupkd3d128 is broken in binutils, so these are hand coded - test_vupkd3d128_d3dcolor: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] - # vupkd3d128 v3, v3, 0 - .long 0x18601FF0 + vupkd3d128 v3, v3, 0 blr #_ REGISTER_OUT v3 [3f800001, 3f800002, 3f800003, 3f800004] test_vupkd3d128_short2_0: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001] - # vupkd3d128 v3, v3, 1 - .long 0x18641FF0 + vupkd3d128 v3, v3, 1 blr - #_ REGISTER_OUT v3 [40407fff, 403f8001, 00000000, 3f800000] + #_ REGISTER_OUT v3 [3F8000FF, 3F800080, 3F800001, 3F80007F] test_vupkd3d128_short2_1: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 4000C000] - # vupkd3d128 v3, v3, 1 - .long 0x18641FF0 + vupkd3d128 v3, v3, 1 blr - #_ REGISTER_OUT v3 [40404000, 403FC000, 00000000, 3f800000] + #_ REGISTER_OUT v3 [3F800000, 3F8000C0, 3F800000, 3F800040] test_vupkd3d128_short2_2: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFFF333] - # vupkd3d128 v3, v3, 1 - .long 0x18641FF0 + vupkd3d128 v3, v3, 1 blr - #_ REGISTER_OUT v3 [40407FFF, 403FF333, 00000000, 3f800000] + #_ REGISTER_OUT v3 [3F8000FF, 3F8000F3, 3F800033, 3F80007F] test_vupkd3d128_short2_3: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00008000] - # vupkd3d128 v3, v3, 1 - .long 0x18641FF0 + vupkd3d128 v3, v3, 1 blr - #_ REGISTER_OUT v3 [40400000, 7FC00000, 00000000, 3f800000] + #_ REGISTER_OUT v3 [3F800000, 3F800080, 3F800000, 3F800000] test_vupkd3d128_short4_0: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, 7FFFFFFF, 007FFFF8] - # vupkd3d128 v3, v3, 4 - .long 0x18701FF0 + vupkd3d128 v3, v3, 4 blr - #_ REGISTER_OUT v3 [40407FFF, 403FFFFF, 4040007F, 403FFFF8] + #_ REGISTER_OUT v3 [4040007F, 403FFFF8, 00000000, 3F800000] test_vupkd3d128_float16_2_0: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3800B800] - # vupkd3d128 v3, v3, 3 - .long 0x186C1FF0 + vupkd3d128 v3, v3, 3 blr - #_ REGISTER_OUT v3 [3F000000, BF000000, 00000000, 3f800000] + #_ REGISTER_OUT v3 [3F800000, 3F8000B8, 3F800000, 3F800038] test_vupkd3d128_float16_4_0: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, 3800B801, 3802B803] - # vupkd3d128 v3, v3, 5 - .long 0x18741FF0 + vupkd3d128 v3, v3, 5 blr - #_ REGISTER_OUT v3 [3F000000, bf002000, 3f004000, bf006000] + #_ REGISTER_OUT v3 [40403802, 403FB803, 00000000, 3F800000] test_vupkd3d128_uint_2101010_0: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 400001FF] - # vupkd3d128 v3, v3, 2 - .long 0x18681FF0 + vupkd3d128 v3, v3, 2 blr - #_ REGISTER_OUT v3 [404001FF, 40400000, 40400000, 3F800001] + #_ REGISTER_OUT v3 [3F800000, 3F800001, 3F8000FF, 3F800040] test_vupkd3d128_uint_2101010_1: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 40000201] - # vupkd3d128 v3, v3, 2 - .long 0x18681FF0 + vupkd3d128 v3, v3, 2 blr - #_ REGISTER_OUT v3 [403FFE01, 40400000, 40400000, 3F800001] + #_ REGISTER_OUT v3 [3F800000, 3F800002, 3F800001, 3F800040] test_vupkd3d128_uint_2101010_2: #_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 40000200] - # vupkd3d128 v3, v3, 2 - .long 0x18681FF0 + vupkd3d128 v3, v3, 2 blr - #_ REGISTER_OUT v3 [7FC00000, 40400000, 40400000, 3F800001] + #_ REGISTER_OUT v3 [3F800000, 3F800002, 3F800000, 3F800040] diff --git a/third_party/binutils/binutils-2.24-vmx128.patch b/third_party/binutils/binutils-2.24-vmx128.patch index 4962db75a..7af22aa69 100644 --- a/third_party/binutils/binutils-2.24-vmx128.patch +++ b/third_party/binutils/binutils-2.24-vmx128.patch @@ -85,13 +85,13 @@ diff -u -P -r opcodes/ppc-opc.c opcodes/ppc-opc.c + { 0xff, 0, insert_vperm, extract_vperm, 0 }, + +#define VD3D0 VPERM128 + 1 -+ { 3, 18, NULL, NULL, 0 }, ++ { 0x7, 18, NULL, NULL, 0 }, + +#define VD3D1 VD3D0 + 1 -+ { 2, 16, NULL, NULL, 0 }, ++ { 0x3, 16, NULL, NULL, 0 }, + +#define VD3D2 VD3D1 + 1 -+ { 2, 6, NULL, NULL, 0 }, ++ { 0x3, 6, NULL, NULL, 0 }, + + /* The SIMM field in a VX form instruction, and TE in Z form. */ +#define SIMM VD3D2 + 1