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[D3D12] Common root constants for EDRAM load/store and single sample load

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This commit is contained in:
Triang3l
2018-08-22 19:54:51 +03:00
parent c4f80aac0d
commit 2d8527c9df
13 changed files with 109 additions and 83 deletions
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11
src/xenia/gpu/d3d12/shaders/edram_load_color_32bpp.cs.hlsl
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@@ -8,16 +8,7 @@ void main(uint3 xe_group_id : SV_GroupID,
tile_dword_index.x *= 4u;
uint4 pixels = xe_edram_load_store_source.Load4(
XeEDRAMOffset(xe_group_id.xy, tile_dword_index));
if (xe_edram_swap_red_blue != 0u) {
// Not a very long shift, just 16 or 20.
uint blue_shift = xe_edram_swap_red_blue >> 16u;
uint red_mask = xe_edram_swap_red_blue & 0xFFFFu;
uint blue_mask = red_mask << blue_shift;
pixels = (pixels & ~(red_mask | blue_mask)) |
((pixels & red_mask) << blue_shift) |
((pixels >> blue_shift) & red_mask);
}
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
xe_edram_load_store_dest.Store4(rt_offset, pixels);
}

7
src/xenia/gpu/d3d12/shaders/edram_load_color_64bpp.cs.hlsl
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@@ -13,12 +13,7 @@ void main(uint3 xe_group_id : SV_GroupID,
}
uint4 pixels = xe_edram_load_store_source.Load4(
XeEDRAMOffset(xe_group_id.xy, tile_dword_index));
if (xe_edram_swap_red_blue != 0u) {
// The only 64-bit formats with a blue component are 16_16_16_16 and
// 16_16_16_16_FLOAT.
pixels = (pixels.yxwz & 0xFFFFu) | (pixels & 0xFFFF0000u);
}
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
xe_edram_load_store_dest.Store4(rt_offset, pixels);
}

6
src/xenia/gpu/d3d12/shaders/edram_load_color_7e3.cs.hlsl
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@@ -14,11 +14,7 @@ void main(uint3 xe_group_id : SV_GroupID,
uint4 pixels_f16u32_packed =
uint4(pixel_0_f16u32.xz, pixel_1_f16u32.xz) |
(uint4(pixel_0_f16u32.yw, pixel_1_f16u32.yw) << 16u);
if (xe_edram_swap_red_blue != 0u) {
pixels_f16u32_packed = (pixels_f16u32_packed.yxwz & 0xFFFFu) |
(pixels_f16u32_packed & 0xFFFF0000u);
}
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
xe_edram_load_store_dest.Store4(rt_offset, pixels_f16u32_packed);
}

6
src/xenia/gpu/d3d12/shaders/edram_load_depth_float.cs.hlsl
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@@ -19,13 +19,13 @@ void main(uint3 xe_group_id : SV_GroupID,
uint4 depth = depth24to32 + (depth32 - depth24to32) *
uint4(XeFloat32To20e4(depth32) == depth24);
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
xe_edram_load_store_dest.Store4(rt_offset, depth);
// Stencil.
uint4 stencil = (depth24_stencil & 0xFFu) << uint4(0u, 8u, 16u, 24u);
stencil.xy |= stencil.zw;
stencil.x |= stencil.y;
rt_offset = xe_edram_rt_stencil_offset +
xe_thread_id.y * xe_edram_rt_stencil_pitch + xe_thread_id.x * 4u;
rt_offset = xe_thread_id.y * xe_edram_rt_stencil_pitch + xe_thread_id.x * 4u +
xe_edram_rt_stencil_offset;
xe_edram_load_store_dest.Store(rt_offset, stencil.x);
}

6
src/xenia/gpu/d3d12/shaders/edram_load_depth_unorm.cs.hlsl
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@@ -10,13 +10,13 @@ void main(uint3 xe_group_id : SV_GroupID,
XeEDRAMOffset(xe_group_id.xy, tile_dword_index));
// Depth.
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
xe_edram_load_store_dest.Store4(rt_offset, pixels >> 8u);
// Stencil.
uint4 stencil = (pixels & 0xFFu) << uint4(0u, 8u, 16u, 24u);
stencil.xy |= stencil.zw;
stencil.x |= stencil.y;
rt_offset = xe_edram_rt_stencil_offset +
xe_thread_id.y * xe_edram_rt_stencil_pitch + xe_thread_id.x * 4u;
rt_offset = xe_thread_id.y * xe_edram_rt_stencil_pitch + xe_thread_id.x * 4u +
xe_edram_rt_stencil_offset;
xe_edram_load_store_dest.Store(rt_offset, stencil.x);
}

42
src/xenia/gpu/d3d12/shaders/edram_load_store.hlsli
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@@ -1,25 +1,43 @@
#ifndef XENIA_GPU_D3D12_SHADERS_EDRAM_LOAD_STORE_HLSLI_
#define XENIA_GPU_D3D12_SHADERS_EDRAM_LOAD_STORE_HLSLI_
// Root constants.
cbuffer XeEDRAMLoadStoreConstants : register(b0) {
uint xe_edram_base_tiles;
uint xe_edram_pitch_tiles;
uint xe_edram_rt_color_depth_pitch;
uint xe_edram_rt_stencil_offset_or_swap_red_blue;
uint xe_edram_rt_stencil_pitch;
uint4 xe_edram_load_store_constants;
// Base in the lower 11 bits, pitch in the upper part, in tiles.
uint xe_edram_base_pitch_tiles;
};
#define xe_edram_rt_stencil_offset xe_edram_rt_stencil_offset_or_swap_red_blue
// For loads only. How exactly it's handled depends on the specific load shader,
// but 0 always means red and blue shouldn't be swapped.
#define xe_edram_swap_red_blue xe_edram_rt_stencil_offset_or_swap_red_blue
// For loading and storing render targets.
#define xe_edram_rt_color_depth_offset (xe_edram_load_store_constants.x)
#define xe_edram_rt_color_depth_pitch (xe_edram_load_store_constants.y)
#define xe_edram_rt_stencil_offset (xe_edram_load_store_constants.z)
#define xe_edram_rt_stencil_pitch (xe_edram_load_store_constants.w)
// For single sample resolving.
// Left/top of the copied region (relative to EDRAM base) in the lower 16 bits,
// right/bottom in the upper.
#define xe_edram_tile_sample_rect (xe_edram_load_store_constants.xy)
#define xe_edram_tile_sample_dest_base (xe_edram_load_store_constants.z)
// 0:13 - destination pitch.
// 14 - log2(vertical sample count), 0 for 1x AA, 1 for 2x/4x AA.
// 15 - log2(horizontal sample count), 0 for 1x/2x AA, 1 for 4x AA.
// 16:17 - sample to load (16 - vertical index, 17 - horizontal index).
// 18:19 - destination endianness.
// 20:31 - BPP-specific info for swapping red/blue, 0 if not swapping.
// For 32 bits per pixel:
// 20:24 - red/blue bit depth.
// 25:29 - blue offset.
// For 64 bits per pixel, it's 1 if need to swap 0:15 and 32:47.
#define xe_edram_tile_sample_dest_info (xe_edram_load_store_constants.w)
ByteAddressBuffer xe_edram_load_store_source : register(t0);
RWByteAddressBuffer xe_edram_load_store_dest : register(u0);
uint XeEDRAMOffset(uint2 tile_index, uint2 tile_dword_index) {
return (xe_edram_base_tiles + (tile_index.y * xe_edram_pitch_tiles) +
tile_index.x) * 5120u + tile_dword_index.y * 320u +
tile_dword_index.x * 4u;
return ((xe_edram_base_pitch_tiles & 2047u) +
tile_index.y * (xe_edram_base_pitch_tiles >> 11u) + tile_index.x) *
5120u + tile_dword_index.y * 320u + tile_dword_index.x * 4u;
}
#endif // XENIA_GPU_D3D12_SHADERS_EDRAM_LOAD_STORE_HLSLI_

2
src/xenia/gpu/d3d12/shaders/edram_store_color_32bpp.cs.hlsl
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@@ -5,7 +5,7 @@ void main(uint3 xe_group_id : SV_GroupID,
uint3 xe_group_thread_id : SV_GroupThreadID,
uint3 xe_thread_id : SV_DispatchThreadID) {
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
uint4 pixels = xe_edram_load_store_source.Load4(rt_offset);
uint2 tile_dword_index = xe_group_thread_id.xy;
tile_dword_index.x *= 4u;

2
src/xenia/gpu/d3d12/shaders/edram_store_color_64bpp.cs.hlsl
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@@ -5,7 +5,7 @@ void main(uint3 xe_group_id : SV_GroupID,
uint3 xe_group_thread_id : SV_GroupThreadID,
uint3 xe_thread_id : SV_DispatchThreadID) {
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
uint4 pixels = xe_edram_load_store_source.Load4(rt_offset);
// One tile contains 80x8 texels, and 2 rows within a 80x16 tile contain data
// from 1 render target row rather than 1. Threads with X 0-19 are for the

2
src/xenia/gpu/d3d12/shaders/edram_store_color_7e3.cs.hlsl
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@@ -6,7 +6,7 @@ void main(uint3 xe_group_id : SV_GroupID,
uint3 xe_group_thread_id : SV_GroupThreadID,
uint3 xe_thread_id : SV_DispatchThreadID) {
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
uint4 pixels_f16u32_packed = xe_edram_load_store_source.Load4(rt_offset);
uint4 pixel_0_f16u32 = pixels_f16u32_packed.xxyy >> uint4(0u, 16u, 0u, 16u);
uint4 pixel_1_f16u32 = pixels_f16u32_packed.zzww >> uint4(0u, 16u, 0u, 16u);

6
src/xenia/gpu/d3d12/shaders/edram_store_depth_float.cs.hlsl
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@@ -7,12 +7,12 @@ void main(uint3 xe_group_id : SV_GroupID,
uint3 xe_thread_id : SV_DispatchThreadID) {
// Depth.
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
uint4 depth32 = xe_edram_load_store_source.Load4(rt_offset);
uint4 depth24_stencil = XeFloat32To20e4(depth32) << 8u;
// Stencil.
rt_offset = xe_edram_rt_stencil_offset +
xe_thread_id.y * xe_edram_rt_stencil_pitch + xe_thread_id.x * 4u;
rt_offset = xe_thread_id.y * xe_edram_rt_stencil_pitch + xe_thread_id.x * 4u +
xe_edram_rt_stencil_offset;
depth24_stencil |= (xe_edram_load_store_source.Load(rt_offset).xxxx >>
uint4(0u, 8u, 16u, 24u)) & 0xFFu;
uint2 tile_dword_index = xe_group_thread_id.xy;

6
src/xenia/gpu/d3d12/shaders/edram_store_depth_unorm.cs.hlsl
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@@ -6,12 +6,12 @@ void main(uint3 xe_group_id : SV_GroupID,
uint3 xe_thread_id : SV_DispatchThreadID) {
// Depth.
uint rt_offset = xe_thread_id.y * xe_edram_rt_color_depth_pitch +
xe_thread_id.x * 16u;
xe_thread_id.x * 16u + xe_edram_rt_color_depth_offset;
uint4 pixels =
(xe_edram_load_store_source.Load4(rt_offset) & 0xFFFFFFu) << 8u;
// Stencil.
rt_offset = xe_edram_rt_stencil_offset +
xe_thread_id.y * xe_edram_rt_stencil_pitch + xe_thread_id.x * 4u;
rt_offset = xe_thread_id.y * xe_edram_rt_stencil_pitch + xe_thread_id.x * 4u +
xe_edram_rt_stencil_offset;
pixels |= (xe_edram_load_store_source.Load(rt_offset).xxxx >>
uint4(0u, 8u, 16u, 24u)) & 0xFFu;
uint2 tile_dword_index = xe_group_thread_id.xy;