Moving cpu/frontend/ppc/ to cpu/frontend/.

src/xenia/cpu/frontend/test/README.md

@@ -0,0 +1,61 @@
+# Codegen Tests
+
+This directory contains the test assets used by the automated codegen test
+runner.
+
+Each test is structured as a source `[name].s` PPC assembly file and the
+generated outputs. The outputs are made using the custom build of binutils
+setup when `xenia-build setup` is called and are checked in to make it easier
+to run the tests on Windows.
+
+Tests are run using the `xenia-test` app or via `xenia-build test`.
+
+## Execution
+
+The test binary is placed into memory at `0x82010000` and all other memory is
+zeroed.
+
+All registers are reset to zero. In order to provide useful inputs tests can
+specify `# REGISTER_IN` values.
+
+The code is jumped into at the starting address and executed until the last
+instruction in the input file is reached.
+
+After all instructions complete any `# REGISTER_OUT` values are checked and if
+they do not match the test is failed.
+
+## Annotations
+
+Annotations can appear at any line in a file. If a number is required it can
+be in either hex or decimal form, or IEEE if floating-point.
+
+### REGISTER_IN
+
+```
+# REGISTER_IN [register name] [register value]
+```
+
+Sets the value of a register prior to executing the instructions.
+
+Examples:
+```
+# REGISTER_IN r4 0x1234
+# REGISTER_IN r4 5678
+```
+
+### REGISTER_OUT
+
+```
+# REGISTER_OUT [register name] [register value]
+```
+
+Defines the expected register value when the instructions have executed.
+If after all instructions have completed the register value does not match
+the value given here the test will fail.
+
+Examples:
+```
+# REGISTER_OUT r3 123
+```
+
+TODO: memory setup/assertions

src/xenia/cpu/frontend/test/bin/instr_add.dis

@@ -0,0 +1,13 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_add.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_add_1>:
+  100000:	7d 65 ca 14 	add     r11,r5,r25
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_add_2>:
+  100008:	7d 60 ca 14 	add     r11,r0,r25
+  10000c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_add.map

@@ -0,0 +1,2 @@
+0000000000000000 t test_add_1
+0000000000000008 t test_add_2

src/xenia/cpu/frontend/test/bin/instr_addc.dis

@@ -0,0 +1,30 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_addc.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_addc_1>:
+  100000:	7c 64 28 14 	addc    r3,r4,r5
+  100004:	7c c0 01 14 	adde    r6,r0,r0
+  100008:	4e 80 00 20 	blr
+
+000000000010000c <test_addc_2>:
+  10000c:	7c 64 28 14 	addc    r3,r4,r5
+  100010:	7c c0 01 14 	adde    r6,r0,r0
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_addc_3>:
+  100018:	7c 64 28 14 	addc    r3,r4,r5
+  10001c:	7c c0 01 14 	adde    r6,r0,r0
+  100020:	4e 80 00 20 	blr
+
+0000000000100024 <test_addc_4>:
+  100024:	7c 64 28 14 	addc    r3,r4,r5
+  100028:	7c c0 01 14 	adde    r6,r0,r0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_addc_5>:
+  100030:	7c 64 28 14 	addc    r3,r4,r5
+  100034:	7c c0 01 14 	adde    r6,r0,r0
+  100038:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_addc.map

@@ -0,0 +1,5 @@
+0000000000000000 t test_addc_1
+000000000000000c t test_addc_2
+0000000000000018 t test_addc_3
+0000000000000024 t test_addc_4
+0000000000000030 t test_addc_5

src/xenia/cpu/frontend/test/bin/instr_adde.dis

@@ -0,0 +1,70 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_adde.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_adde_1>:
+  100000:	7c 64 29 14 	adde    r3,r4,r5
+  100004:	7c c0 01 14 	adde    r6,r0,r0
+  100008:	4e 80 00 20 	blr
+
+000000000010000c <test_adde_2>:
+  10000c:	7c 63 1a 78 	xor     r3,r3,r3
+  100010:	7c 63 18 f8 	not     r3,r3
+  100014:	30 63 00 01 	addic   r3,r3,1
+  100018:	7c 64 29 14 	adde    r3,r4,r5
+  10001c:	7c c0 01 14 	adde    r6,r0,r0
+  100020:	4e 80 00 20 	blr
+
+0000000000100024 <test_adde_3>:
+  100024:	7c 64 29 14 	adde    r3,r4,r5
+  100028:	7c c0 01 14 	adde    r6,r0,r0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_adde_4>:
+  100030:	7c 63 1a 78 	xor     r3,r3,r3
+  100034:	7c 63 18 f8 	not     r3,r3
+  100038:	30 63 00 01 	addic   r3,r3,1
+  10003c:	7c 64 29 14 	adde    r3,r4,r5
+  100040:	7c c0 01 14 	adde    r6,r0,r0
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_adde_5>:
+  100048:	7c 64 29 14 	adde    r3,r4,r5
+  10004c:	7c c0 01 14 	adde    r6,r0,r0
+  100050:	4e 80 00 20 	blr
+
+0000000000100054 <test_adde_6>:
+  100054:	7c 63 1a 78 	xor     r3,r3,r3
+  100058:	7c 63 18 f8 	not     r3,r3
+  10005c:	30 63 00 01 	addic   r3,r3,1
+  100060:	7c 64 29 14 	adde    r3,r4,r5
+  100064:	7c c0 01 14 	adde    r6,r0,r0
+  100068:	4e 80 00 20 	blr
+
+000000000010006c <test_adde_7>:
+  10006c:	7c 64 29 14 	adde    r3,r4,r5
+  100070:	7c c0 01 14 	adde    r6,r0,r0
+  100074:	4e 80 00 20 	blr
+
+0000000000100078 <test_adde_8>:
+  100078:	7c 63 1a 78 	xor     r3,r3,r3
+  10007c:	7c 63 18 f8 	not     r3,r3
+  100080:	30 63 00 01 	addic   r3,r3,1
+  100084:	7c 64 29 14 	adde    r3,r4,r5
+  100088:	7c c0 01 14 	adde    r6,r0,r0
+  10008c:	4e 80 00 20 	blr
+
+0000000000100090 <test_adde_9>:
+  100090:	7c 64 29 14 	adde    r3,r4,r5
+  100094:	7c c0 01 14 	adde    r6,r0,r0
+  100098:	4e 80 00 20 	blr
+
+000000000010009c <test_adde_10>:
+  10009c:	7c 63 1a 78 	xor     r3,r3,r3
+  1000a0:	7c 63 18 f8 	not     r3,r3
+  1000a4:	30 63 00 01 	addic   r3,r3,1
+  1000a8:	7c 64 29 14 	adde    r3,r4,r5
+  1000ac:	7c c0 01 14 	adde    r6,r0,r0
+  1000b0:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_adde.map

@@ -0,0 +1,10 @@
+0000000000000000 t test_adde_1
+000000000000000c t test_adde_2
+0000000000000024 t test_adde_3
+0000000000000030 t test_adde_4
+0000000000000048 t test_adde_5
+0000000000000054 t test_adde_6
+000000000000006c t test_adde_7
+0000000000000078 t test_adde_8
+0000000000000090 t test_adde_9
+000000000000009c t test_adde_10

src/xenia/cpu/frontend/test/bin/instr_addic.dis

@@ -0,0 +1,15 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_addic.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_addic_1>:
+  100000:	30 84 00 01 	addic   r4,r4,1
+  100004:	7c c0 01 14 	adde    r6,r0,r0
+  100008:	4e 80 00 20 	blr
+
+000000000010000c <test_addic_2>:
+  10000c:	30 84 00 01 	addic   r4,r4,1
+  100010:	7c c0 01 14 	adde    r6,r0,r0
+  100014:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_addic.map

@@ -0,0 +1,2 @@
+0000000000000000 t test_addic_1
+000000000000000c t test_addic_2

src/xenia/cpu/frontend/test/bin/instr_addme.dis

@@ -0,0 +1,57 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_addme.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_addme_1>:
+  100000:	7c 64 01 d4 	addme   r3,r4
+  100004:	7c c0 01 14 	adde    r6,r0,r0
+  100008:	4e 80 00 20 	blr
+
+000000000010000c <test_addme_2>:
+  10000c:	7c 63 1a 78 	xor     r3,r3,r3
+  100010:	7c 63 18 f8 	not     r3,r3
+  100014:	30 63 00 01 	addic   r3,r3,1
+  100018:	7c 64 01 d4 	addme   r3,r4
+  10001c:	7c c0 01 14 	adde    r6,r0,r0
+  100020:	4e 80 00 20 	blr
+
+0000000000100024 <test_addme_3>:
+  100024:	7c 64 01 d4 	addme   r3,r4
+  100028:	7c c0 01 14 	adde    r6,r0,r0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_addme_4>:
+  100030:	7c 63 1a 78 	xor     r3,r3,r3
+  100034:	7c 63 18 f8 	not     r3,r3
+  100038:	30 63 00 01 	addic   r3,r3,1
+  10003c:	7c 64 01 d4 	addme   r3,r4
+  100040:	7c c0 01 14 	adde    r6,r0,r0
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_addme_5>:
+  100048:	7c 64 01 d4 	addme   r3,r4
+  10004c:	7c c0 01 14 	adde    r6,r0,r0
+  100050:	4e 80 00 20 	blr
+
+0000000000100054 <test_addme_6>:
+  100054:	7c 63 1a 78 	xor     r3,r3,r3
+  100058:	7c 63 18 f8 	not     r3,r3
+  10005c:	30 63 00 01 	addic   r3,r3,1
+  100060:	7c 64 01 d4 	addme   r3,r4
+  100064:	7c c0 01 14 	adde    r6,r0,r0
+  100068:	4e 80 00 20 	blr
+
+000000000010006c <test_addme_7>:
+  10006c:	7c 64 01 d4 	addme   r3,r4
+  100070:	7c c0 01 14 	adde    r6,r0,r0
+  100074:	4e 80 00 20 	blr
+
+0000000000100078 <test_addme_8>:
+  100078:	7c 63 1a 78 	xor     r3,r3,r3
+  10007c:	7c 63 18 f8 	not     r3,r3
+  100080:	30 63 00 01 	addic   r3,r3,1
+  100084:	7c 64 01 d4 	addme   r3,r4
+  100088:	7c c0 01 14 	adde    r6,r0,r0
+  10008c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_addme.map

@@ -0,0 +1,8 @@
+0000000000000000 t test_addme_1
+000000000000000c t test_addme_2
+0000000000000024 t test_addme_3
+0000000000000030 t test_addme_4
+0000000000000048 t test_addme_5
+0000000000000054 t test_addme_6
+000000000000006c t test_addme_7
+0000000000000078 t test_addme_8

src/xenia/cpu/frontend/test/bin/instr_addze.dis

@@ -0,0 +1,57 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_addze.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_addze_1>:
+  100000:	7c 64 01 94 	addze   r3,r4
+  100004:	7c c0 01 14 	adde    r6,r0,r0
+  100008:	4e 80 00 20 	blr
+
+000000000010000c <test_addze_2>:
+  10000c:	7c 63 1a 78 	xor     r3,r3,r3
+  100010:	7c 63 18 f8 	not     r3,r3
+  100014:	30 63 00 01 	addic   r3,r3,1
+  100018:	7c 64 01 94 	addze   r3,r4
+  10001c:	7c c0 01 14 	adde    r6,r0,r0
+  100020:	4e 80 00 20 	blr
+
+0000000000100024 <test_addze_3>:
+  100024:	7c 64 01 94 	addze   r3,r4
+  100028:	7c c0 01 14 	adde    r6,r0,r0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_addze_4>:
+  100030:	7c 63 1a 78 	xor     r3,r3,r3
+  100034:	7c 63 18 f8 	not     r3,r3
+  100038:	30 63 00 01 	addic   r3,r3,1
+  10003c:	7c 64 01 94 	addze   r3,r4
+  100040:	7c c0 01 14 	adde    r6,r0,r0
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_addze_5>:
+  100048:	7c 64 01 94 	addze   r3,r4
+  10004c:	7c c0 01 14 	adde    r6,r0,r0
+  100050:	4e 80 00 20 	blr
+
+0000000000100054 <test_addze_6>:
+  100054:	7c 63 1a 78 	xor     r3,r3,r3
+  100058:	7c 63 18 f8 	not     r3,r3
+  10005c:	30 63 00 01 	addic   r3,r3,1
+  100060:	7c 64 01 94 	addze   r3,r4
+  100064:	7c c0 01 14 	adde    r6,r0,r0
+  100068:	4e 80 00 20 	blr
+
+000000000010006c <test_addze_7>:
+  10006c:	7c 64 01 94 	addze   r3,r4
+  100070:	7c c0 01 14 	adde    r6,r0,r0
+  100074:	4e 80 00 20 	blr
+
+0000000000100078 <test_addze_8>:
+  100078:	7c 63 1a 78 	xor     r3,r3,r3
+  10007c:	7c 63 18 f8 	not     r3,r3
+  100080:	30 63 00 01 	addic   r3,r3,1
+  100084:	7c 64 01 94 	addze   r3,r4
+  100088:	7c c0 01 14 	adde    r6,r0,r0
+  10008c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_addze.map

@@ -0,0 +1,8 @@
+0000000000000000 t test_addze_1
+000000000000000c t test_addze_2
+0000000000000024 t test_addze_3
+0000000000000030 t test_addze_4
+0000000000000048 t test_addze_5
+0000000000000054 t test_addze_6
+000000000000006c t test_addze_7
+0000000000000078 t test_addze_8

src/xenia/cpu/frontend/test/bin/instr_cntlzd.dis

@@ -0,0 +1,21 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_cntlzd.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_cntlzd_1>:
+  100000:	7c a6 00 74 	cntlzd  r6,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_cntlzd_2>:
+  100008:	7c a6 00 74 	cntlzd  r6,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_cntlzd_3>:
+  100010:	7c a6 00 74 	cntlzd  r6,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_cntlzd_4>:
+  100018:	7c a6 00 74 	cntlzd  r6,r5
+  10001c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_cntlzd.map

@@ -0,0 +1,4 @@
+0000000000000000 t test_cntlzd_1
+0000000000000008 t test_cntlzd_2
+0000000000000010 t test_cntlzd_3
+0000000000000018 t test_cntlzd_4

src/xenia/cpu/frontend/test/bin/instr_cntlzw.dis

@@ -0,0 +1,21 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_cntlzw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_cntlzw_1>:
+  100000:	7c a6 00 34 	cntlzw  r6,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_cntlzw_2>:
+  100008:	7c a6 00 34 	cntlzw  r6,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_cntlzw_3>:
+  100010:	7c a6 00 34 	cntlzw  r6,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_cntlzw_4>:
+  100018:	7c a6 00 34 	cntlzw  r6,r5
+  10001c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_cntlzw.map

@@ -0,0 +1,4 @@
+0000000000000000 t test_cntlzw_1
+0000000000000008 t test_cntlzw_2
+0000000000000010 t test_cntlzw_3
+0000000000000018 t test_cntlzw_4

src/xenia/cpu/frontend/test/bin/instr_divd.dis

@@ -0,0 +1,33 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_divd.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_divd_1>:
+  100000:	7c 64 2b d2 	divd    r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_divd_3>:
+  100008:	7c 64 2b d2 	divd    r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_divd_4>:
+  100010:	7c 64 2b d2 	divd    r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_divd_5>:
+  100018:	7c 64 2b d2 	divd    r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_divd_6>:
+  100020:	7c 64 2b d2 	divd    r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_divd_7>:
+  100028:	7c 64 2b d2 	divd    r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_divd_8>:
+  100030:	7c 64 2b d2 	divd    r3,r4,r5
+  100034:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_divd.map

@@ -0,0 +1,7 @@
+0000000000000000 t test_divd_1
+0000000000000008 t test_divd_3
+0000000000000010 t test_divd_4
+0000000000000018 t test_divd_5
+0000000000000020 t test_divd_6
+0000000000000028 t test_divd_7
+0000000000000030 t test_divd_8

src/xenia/cpu/frontend/test/bin/instr_divdu.dis

@@ -0,0 +1,37 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_divdu.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_divdu_1>:
+  100000:	7c 64 2b 92 	divdu   r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_divdu_3>:
+  100008:	7c 64 2b 92 	divdu   r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_divdu_4>:
+  100010:	7c 64 2b 92 	divdu   r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_divdu_5>:
+  100018:	7c 64 2b 92 	divdu   r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_divdu_6>:
+  100020:	7c 64 2b 92 	divdu   r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_divdu_7>:
+  100028:	7c 64 2b 92 	divdu   r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_divdu_8>:
+  100030:	7c 64 2b 92 	divdu   r3,r4,r5
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_divdu_9>:
+  100038:	7c 64 2b 92 	divdu   r3,r4,r5
+  10003c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_divdu.map

@@ -0,0 +1,8 @@
+0000000000000000 t test_divdu_1
+0000000000000008 t test_divdu_3
+0000000000000010 t test_divdu_4
+0000000000000018 t test_divdu_5
+0000000000000020 t test_divdu_6
+0000000000000028 t test_divdu_7
+0000000000000030 t test_divdu_8
+0000000000000038 t test_divdu_9

src/xenia/cpu/frontend/test/bin/instr_divw.dis

@@ -0,0 +1,45 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_divw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_divw_1>:
+  100000:	7c 64 2b d6 	divw    r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_divw_3>:
+  100008:	7c 64 2b d6 	divw    r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_divw_4>:
+  100010:	7c 64 2b d6 	divw    r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_divw_5>:
+  100018:	7c 64 2b d6 	divw    r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_divw_6>:
+  100020:	7c 64 2b d6 	divw    r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_divw_7>:
+  100028:	7c 64 2b d6 	divw    r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_divw_8>:
+  100030:	7c 64 2b d6 	divw    r3,r4,r5
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_divw_9>:
+  100038:	7c 64 2b d6 	divw    r3,r4,r5
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_divw_10>:
+  100040:	7c 64 2b d6 	divw    r3,r4,r5
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_divw_11>:
+  100048:	7c 64 2b d6 	divw    r3,r4,r5
+  10004c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_divw.map

@@ -0,0 +1,10 @@
+0000000000000000 t test_divw_1
+0000000000000008 t test_divw_3
+0000000000000010 t test_divw_4
+0000000000000018 t test_divw_5
+0000000000000020 t test_divw_6
+0000000000000028 t test_divw_7
+0000000000000030 t test_divw_8
+0000000000000038 t test_divw_9
+0000000000000040 t test_divw_10
+0000000000000048 t test_divw_11

src/xenia/cpu/frontend/test/bin/instr_divwu.dis

@@ -0,0 +1,49 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_divwu.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_divwu_1>:
+  100000:	7c 64 2b 96 	divwu   r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_divwu_3>:
+  100008:	7c 64 2b 96 	divwu   r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_divwu_4>:
+  100010:	7c 64 2b 96 	divwu   r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_divwu_5>:
+  100018:	7c 64 2b 96 	divwu   r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_divwu_6>:
+  100020:	7c 64 2b 96 	divwu   r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_divwu_7>:
+  100028:	7c 64 2b 96 	divwu   r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_divwu_8>:
+  100030:	7c 64 2b 96 	divwu   r3,r4,r5
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_divwu_9>:
+  100038:	7c 64 2b 96 	divwu   r3,r4,r5
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_divwu_10>:
+  100040:	7c 64 2b 96 	divwu   r3,r4,r5
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_divwu_11>:
+  100048:	7c 64 2b 96 	divwu   r3,r4,r5
+  10004c:	4e 80 00 20 	blr
+
+0000000000100050 <test_divwu_12>:
+  100050:	7c 64 2b 96 	divwu   r3,r4,r5
+  100054:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_divwu.map

@@ -0,0 +1,11 @@
+0000000000000000 t test_divwu_1
+0000000000000008 t test_divwu_3
+0000000000000010 t test_divwu_4
+0000000000000018 t test_divwu_5
+0000000000000020 t test_divwu_6
+0000000000000028 t test_divwu_7
+0000000000000030 t test_divwu_8
+0000000000000038 t test_divwu_9
+0000000000000040 t test_divwu_10
+0000000000000048 t test_divwu_11
+0000000000000050 t test_divwu_12

src/xenia/cpu/frontend/test/bin/instr_eqv.dis

@@ -0,0 +1,29 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_eqv.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_eqv_1>:
+  100000:	7c 83 2a 38 	eqv     r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_eqv_2>:
+  100008:	7c 83 2a 38 	eqv     r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_eqv_3>:
+  100010:	7c 83 2a 38 	eqv     r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_eqv_4>:
+  100018:	7c 83 2a 38 	eqv     r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_eqv_5>:
+  100020:	7c 83 2a 38 	eqv     r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_eqv_6>:
+  100028:	7c 83 2a 38 	eqv     r3,r4,r5
+  10002c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_eqv.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_eqv_1
+0000000000000008 t test_eqv_2
+0000000000000010 t test_eqv_3
+0000000000000018 t test_eqv_4
+0000000000000020 t test_eqv_5
+0000000000000028 t test_eqv_6

src/xenia/cpu/frontend/test/bin/instr_fabs.dis

@@ -0,0 +1,17 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_fabs.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_fabs_1>:
+  100000:	fc 20 0a 10 	fabs    f1,f1
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_fabs_2>:
+  100008:	fc 20 0a 10 	fabs    f1,f1
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_fabs_3>:
+  100010:	fc 20 0a 10 	fabs    f1,f1
+  100014:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_fabs.map

@@ -0,0 +1,3 @@
+0000000000000000 t test_fabs_1
+0000000000000008 t test_fabs_2
+0000000000000010 t test_fabs_3

src/xenia/cpu/frontend/test/bin/instr_fsel.dis

@@ -0,0 +1,17 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_fsel.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_fsel_1>:
+  100000:	fc 22 20 ee 	fsel    f1,f2,f3,f4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_fsel_2>:
+  100008:	fc 22 20 ee 	fsel    f1,f2,f3,f4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_fsel_3>:
+  100010:	fc 22 20 ee 	fsel    f1,f2,f3,f4
+  100014:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_fsel.map

@@ -0,0 +1,3 @@
+0000000000000000 t test_fsel_1
+0000000000000008 t test_fsel_2
+0000000000000010 t test_fsel_3

src/xenia/cpu/frontend/test/bin/instr_lvexx.dis

@@ -0,0 +1,29 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvexx.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_lvebx_1>:
+  100000:	7c 60 20 0e 	lvebx   v3,0,r4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_lvebx_2>:
+  100008:	7c 60 20 0e 	lvebx   v3,0,r4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_lvehx_1>:
+  100010:	7c 60 20 4e 	lvehx   v3,0,r4
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_lvehx_2>:
+  100018:	7c 60 20 4e 	lvehx   v3,0,r4
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_lvewx_1>:
+  100020:	7c 60 20 8e 	lvewx   v3,0,r4
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_lvewx_2>:
+  100028:	7c 60 20 8e 	lvewx   v3,0,r4
+  10002c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_lvexx.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_lvebx_1
+0000000000000008 t test_lvebx_2
+0000000000000010 t test_lvehx_1
+0000000000000018 t test_lvehx_2
+0000000000000020 t test_lvewx_1
+0000000000000028 t test_lvewx_2

src/xenia/cpu/frontend/test/bin/instr_lvl.dis

@@ -0,0 +1,9 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvl.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_lvl_1>:
+  100000:	7c 64 04 0e 	lvlx    v3,r4,r0
+  100004:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_lvl.map

@@ -0,0 +1 @@
+0000000000000000 t test_lvl_1

src/xenia/cpu/frontend/test/bin/instr_lvr.dis

@@ -0,0 +1,9 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvr.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_lvr_1>:
+  100000:	7c 64 2c 4e 	lvrx    v3,r4,r5
+  100004:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_lvr.map

@@ -0,0 +1 @@
+0000000000000000 t test_lvr_1

src/xenia/cpu/frontend/test/bin/instr_lvsl.dis

@@ -0,0 +1,17 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvsl.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_lvsl_1>:
+  100000:	7c 64 00 0c 	lvsl    v3,r4,r0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_lvsl_2>:
+  100008:	7c 64 00 0c 	lvsl    v3,r4,r0
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_lvsl_3>:
+  100010:	7c 64 00 0c 	lvsl    v3,r4,r0
+  100014:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_lvsl.map

@@ -0,0 +1,3 @@
+0000000000000000 t test_lvsl_1
+0000000000000008 t test_lvsl_2
+0000000000000010 t test_lvsl_3

src/xenia/cpu/frontend/test/bin/instr_lvsr.dis

@@ -0,0 +1,17 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvsr.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_lvsr_1>:
+  100000:	7c 64 00 4c 	lvsr    v3,r4,r0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_lvsr_2>:
+  100008:	7c 64 00 4c 	lvsr    v3,r4,r0
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_lvsr_3>:
+  100010:	7c 64 00 4c 	lvsr    v3,r4,r0
+  100014:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_lvsr.map

@@ -0,0 +1,3 @@
+0000000000000000 t test_lvsr_1
+0000000000000008 t test_lvsr_2
+0000000000000010 t test_lvsr_3

src/xenia/cpu/frontend/test/bin/instr_mulhd.dis

@@ -0,0 +1,25 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulhd.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_mulhd_1>:
+  100000:	7c 64 28 92 	mulhd   r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_mulhd_2>:
+  100008:	7c 64 28 92 	mulhd   r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_mulhd_3>:
+  100010:	7c 64 28 92 	mulhd   r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_mulhd_4>:
+  100018:	7c 64 28 92 	mulhd   r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_mulhd_5>:
+  100020:	7c 64 28 92 	mulhd   r3,r4,r5
+  100024:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_mulhd.map

@@ -0,0 +1,5 @@
+0000000000000000 t test_mulhd_1
+0000000000000008 t test_mulhd_2
+0000000000000010 t test_mulhd_3
+0000000000000018 t test_mulhd_4
+0000000000000020 t test_mulhd_5

src/xenia/cpu/frontend/test/bin/instr_mulhdu.dis

@@ -0,0 +1,25 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulhdu.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_mulhdu_1>:
+  100000:	7c 64 28 12 	mulhdu  r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_mulhdu_2>:
+  100008:	7c 64 28 12 	mulhdu  r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_mulhdu_3>:
+  100010:	7c 64 28 12 	mulhdu  r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_mulhdu_4>:
+  100018:	7c 64 28 12 	mulhdu  r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_mulhdu_5>:
+  100020:	7c 64 28 12 	mulhdu  r3,r4,r5
+  100024:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_mulhdu.map

@@ -0,0 +1,5 @@
+0000000000000000 t test_mulhdu_1
+0000000000000008 t test_mulhdu_2
+0000000000000010 t test_mulhdu_3
+0000000000000018 t test_mulhdu_4
+0000000000000020 t test_mulhdu_5

src/xenia/cpu/frontend/test/bin/instr_mulhw.dis

@@ -0,0 +1,29 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulhw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_mulhw_1>:
+  100000:	7c 64 28 96 	mulhw   r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_mulhw_2>:
+  100008:	7c 64 28 96 	mulhw   r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_mulhw_3>:
+  100010:	7c 64 28 96 	mulhw   r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_mulhw_4>:
+  100018:	7c 64 28 96 	mulhw   r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_mulhw_5>:
+  100020:	7c 64 28 96 	mulhw   r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_mulhw_6>:
+  100028:	7c 64 28 96 	mulhw   r3,r4,r5
+  10002c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_mulhw.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_mulhw_1
+0000000000000008 t test_mulhw_2
+0000000000000010 t test_mulhw_3
+0000000000000018 t test_mulhw_4
+0000000000000020 t test_mulhw_5
+0000000000000028 t test_mulhw_6

src/xenia/cpu/frontend/test/bin/instr_mulhwu.dis

@@ -0,0 +1,29 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulhwu.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_mulhwu_1>:
+  100000:	7c 64 28 16 	mulhwu  r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_mulhwu_2>:
+  100008:	7c 64 28 16 	mulhwu  r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_mulhwu_3>:
+  100010:	7c 64 28 16 	mulhwu  r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_mulhwu_4>:
+  100018:	7c 64 28 16 	mulhwu  r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_mulhwu_5>:
+  100020:	7c 64 28 16 	mulhwu  r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_mulhwu_6>:
+  100028:	7c 64 28 16 	mulhwu  r3,r4,r5
+  10002c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_mulhwu.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_mulhwu_1
+0000000000000008 t test_mulhwu_2
+0000000000000010 t test_mulhwu_3
+0000000000000018 t test_mulhwu_4
+0000000000000020 t test_mulhwu_5
+0000000000000028 t test_mulhwu_6

src/xenia/cpu/frontend/test/bin/instr_mulld.dis

@@ -0,0 +1,37 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulld.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_mulld_1>:
+  100000:	7c 64 29 d2 	mulld   r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_mulld_2>:
+  100008:	7c 64 29 d2 	mulld   r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_mulld_3>:
+  100010:	7c 64 29 d2 	mulld   r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_mulld_4>:
+  100018:	7c 64 29 d2 	mulld   r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_mulld_5>:
+  100020:	7c 64 29 d2 	mulld   r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_mulld_6>:
+  100028:	7c 64 29 d2 	mulld   r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_mulld_7>:
+  100030:	7c 64 29 d2 	mulld   r3,r4,r5
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_mulld_8>:
+  100038:	7c 64 29 d2 	mulld   r3,r4,r5
+  10003c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_mulld.map

@@ -0,0 +1,8 @@
+0000000000000000 t test_mulld_1
+0000000000000008 t test_mulld_2
+0000000000000010 t test_mulld_3
+0000000000000018 t test_mulld_4
+0000000000000020 t test_mulld_5
+0000000000000028 t test_mulld_6
+0000000000000030 t test_mulld_7
+0000000000000038 t test_mulld_8

src/xenia/cpu/frontend/test/bin/instr_mulli.dis

@@ -0,0 +1,37 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulli.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_mulli_1>:
+  100000:	1c 64 00 00 	mulli   r3,r4,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_mulli_2>:
+  100008:	1c 64 00 01 	mulli   r3,r4,1
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_mulli_3>:
+  100010:	1c 64 ff ff 	mulli   r3,r4,-1
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_mulli_4>:
+  100018:	1c 64 ff ff 	mulli   r3,r4,-1
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_mulli_5>:
+  100020:	1c 64 00 01 	mulli   r3,r4,1
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_mulli_6>:
+  100028:	1c 64 00 02 	mulli   r3,r4,2
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_mulli_7>:
+  100030:	1c 64 ff ff 	mulli   r3,r4,-1
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_mulli_8>:
+  100038:	1c 64 ff ff 	mulli   r3,r4,-1
+  10003c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_mulli.map

@@ -0,0 +1,8 @@
+0000000000000000 t test_mulli_1
+0000000000000008 t test_mulli_2
+0000000000000010 t test_mulli_3
+0000000000000018 t test_mulli_4
+0000000000000020 t test_mulli_5
+0000000000000028 t test_mulli_6
+0000000000000030 t test_mulli_7
+0000000000000038 t test_mulli_8

src/xenia/cpu/frontend/test/bin/instr_mullw.dis

@@ -0,0 +1,49 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_mullw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_mullw_1>:
+  100000:	7c 64 29 d6 	mullw   r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_mullw_2>:
+  100008:	7c 64 29 d6 	mullw   r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_mullw_3>:
+  100010:	7c 64 29 d6 	mullw   r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_mullw_4>:
+  100018:	7c 64 29 d6 	mullw   r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_mullw_5>:
+  100020:	7c 64 29 d6 	mullw   r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_mullw_6>:
+  100028:	7c 64 29 d6 	mullw   r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_mullw_7>:
+  100030:	7c 64 29 d6 	mullw   r3,r4,r5
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_mullw_8>:
+  100038:	7c 64 29 d6 	mullw   r3,r4,r5
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_mullw_9>:
+  100040:	7c 64 29 d6 	mullw   r3,r4,r5
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_mullw_10>:
+  100048:	7c 64 29 d6 	mullw   r3,r4,r5
+  10004c:	4e 80 00 20 	blr
+
+0000000000100050 <test_mullw_11>:
+  100050:	7c 64 29 d6 	mullw   r3,r4,r5
+  100054:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_mullw.map

@@ -0,0 +1,11 @@
+0000000000000000 t test_mullw_1
+0000000000000008 t test_mullw_2
+0000000000000010 t test_mullw_3
+0000000000000018 t test_mullw_4
+0000000000000020 t test_mullw_5
+0000000000000028 t test_mullw_6
+0000000000000030 t test_mullw_7
+0000000000000038 t test_mullw_8
+0000000000000040 t test_mullw_9
+0000000000000048 t test_mullw_10
+0000000000000050 t test_mullw_11

src/xenia/cpu/frontend/test/bin/instr_neg.dis

@@ -0,0 +1,17 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_neg.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_neg_1>:
+  100000:	7c 63 00 d0 	neg     r3,r3
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_neg_2>:
+  100008:	7c 63 00 d0 	neg     r3,r3
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_neg_3>:
+  100010:	7c 63 00 d0 	neg     r3,r3
+  100014:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_neg.map

@@ -0,0 +1,3 @@
+0000000000000000 t test_neg_1
+0000000000000008 t test_neg_2
+0000000000000010 t test_neg_3

src/xenia/cpu/frontend/test/bin/instr_nor.dis

@@ -0,0 +1,14 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_nor.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_nor_cr_1>:
+  100000:	7c 63 18 f9 	not.    r3,r3
+  100004:	38 60 00 00 	li      r3,0
+  100008:	40 82 00 08 	bne     100010 <.nor_cr_1_ne>
+  10000c:	38 60 00 01 	li      r3,1
+
+0000000000100010 <.nor_cr_1_ne>:
+  100010:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_nor.map

@@ -0,0 +1,2 @@
+0000000000000000 t test_nor_cr_1
+0000000000000010 t .nor_cr_1_ne

src/xenia/cpu/frontend/test/bin/instr_ori.dis

@@ -0,0 +1,13 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_ori.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_ori_1>:
+  100000:	60 83 fe dc 	ori     r3,r4,65244
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_ori_2>:
+  100008:	60 83 fe dc 	ori     r3,r4,65244
+  10000c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_ori.map

@@ -0,0 +1,2 @@
+0000000000000000 t test_ori_1
+0000000000000008 t test_ori_2

src/xenia/cpu/frontend/test/bin/instr_rldicl.dis

@@ -0,0 +1,65 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_rldicl.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_rldicl_1>:
+  100000:	78 83 c0 00 	rotldi  r3,r4,24
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_rldicl_2>:
+  100008:	78 83 c2 00 	rldicl  r3,r4,24,8
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_rldicl_3>:
+  100010:	78 83 c7 e0 	rldicl  r3,r4,24,63
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_rldicl_4>:
+  100018:	78 83 00 00 	rotldi  r3,r4,0
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_rldicl_5>:
+  100020:	78 83 07 e0 	clrldi  r3,r4,63
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_rldicl_6>:
+  100028:	78 83 02 00 	clrldi  r3,r4,8
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_rldicl_7>:
+  100030:	78 83 f8 02 	rotldi  r3,r4,63
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_rldicl_8>:
+  100038:	78 83 ff e2 	rldicl  r3,r4,63,63
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_rldicl_9>:
+  100040:	78 83 f8 00 	rotldi  r3,r4,31
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_rldicl_10>:
+  100048:	78 83 d1 82 	rldicl  r3,r4,58,6
+  10004c:	4e 80 00 20 	blr
+
+0000000000100050 <test_srdi_1>:
+  100050:	78 63 00 00 	rotldi  r3,r3,0
+  100054:	78 84 00 00 	rotldi  r4,r4,0
+  100058:	4e 80 00 20 	blr
+
+000000000010005c <test_srdi_2>:
+  10005c:	78 63 f8 42 	rldicl  r3,r3,63,1
+  100060:	78 84 f8 42 	rldicl  r4,r4,63,1
+  100064:	4e 80 00 20 	blr
+
+0000000000100068 <test_srdi_3>:
+  100068:	78 63 00 22 	rldicl  r3,r3,32,32
+  10006c:	78 84 00 22 	rldicl  r4,r4,32,32
+  100070:	4e 80 00 20 	blr
+
+0000000000100074 <test_srdi_4>:
+  100074:	78 63 0f e0 	rldicl  r3,r3,1,63
+  100078:	78 84 0f e0 	rldicl  r4,r4,1,63
+  10007c:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_rldicl.map

@@ -0,0 +1,14 @@
+0000000000000000 t test_rldicl_1
+0000000000000008 t test_rldicl_2
+0000000000000010 t test_rldicl_3
+0000000000000018 t test_rldicl_4
+0000000000000020 t test_rldicl_5
+0000000000000028 t test_rldicl_6
+0000000000000030 t test_rldicl_7
+0000000000000038 t test_rldicl_8
+0000000000000040 t test_rldicl_9
+0000000000000048 t test_rldicl_10
+0000000000000050 t test_srdi_1
+000000000000005c t test_srdi_2
+0000000000000068 t test_srdi_3
+0000000000000074 t test_srdi_4

src/xenia/cpu/frontend/test/bin/instr_rldicr.dis

@@ -0,0 +1,61 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_rldicr.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_rldicr_1>:
+  100000:	78 83 c0 04 	rldicr  r3,r4,24,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_rldicr_2>:
+  100008:	78 83 c2 04 	rldicr  r3,r4,24,8
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_rldicr_3>:
+  100010:	78 83 c7 e4 	rldicr  r3,r4,24,63
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_rldicr_4>:
+  100018:	78 83 00 04 	rldicr  r3,r4,0,0
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_rldicr_5>:
+  100020:	78 83 07 e4 	rldicr  r3,r4,0,63
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_rldicr_6>:
+  100028:	78 83 02 04 	rldicr  r3,r4,0,8
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_rldicr_7>:
+  100030:	78 83 f8 06 	rldicr  r3,r4,63,0
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_rldicr_8>:
+  100038:	78 83 ff e6 	rldicr  r3,r4,63,63
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_rldicr_9>:
+  100040:	78 83 f8 04 	rldicr  r3,r4,31,0
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_sldi_1>:
+  100048:	78 63 07 e4 	rldicr  r3,r3,0,63
+  10004c:	78 84 07 e4 	rldicr  r4,r4,0,63
+  100050:	4e 80 00 20 	blr
+
+0000000000100054 <test_sldi_2>:
+  100054:	78 63 0f a4 	rldicr  r3,r3,1,62
+  100058:	78 84 0f a4 	rldicr  r4,r4,1,62
+  10005c:	4e 80 00 20 	blr
+
+0000000000100060 <test_sldi_3>:
+  100060:	78 63 07 c6 	rldicr  r3,r3,32,31
+  100064:	78 84 07 c6 	rldicr  r4,r4,32,31
+  100068:	4e 80 00 20 	blr
+
+000000000010006c <test_sldi_4>:
+  10006c:	78 63 f8 06 	rldicr  r3,r3,63,0
+  100070:	78 84 f8 06 	rldicr  r4,r4,63,0
+  100074:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_rldicr.map

@@ -0,0 +1,13 @@
+0000000000000000 t test_rldicr_1
+0000000000000008 t test_rldicr_2
+0000000000000010 t test_rldicr_3
+0000000000000018 t test_rldicr_4
+0000000000000020 t test_rldicr_5
+0000000000000028 t test_rldicr_6
+0000000000000030 t test_rldicr_7
+0000000000000038 t test_rldicr_8
+0000000000000040 t test_rldicr_9
+0000000000000048 t test_sldi_1
+0000000000000054 t test_sldi_2
+0000000000000060 t test_sldi_3
+000000000000006c t test_sldi_4

src/xenia/cpu/frontend/test/bin/instr_rlwimi.dis

@@ -0,0 +1,9 @@
+
+/vagrant/src/xenia/cpu/frontend/test/bin//instr_rlwimi.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_rlwimi>:
+  100000:	50 86 10 3a 	rlwimi  r6,r4,2,0,29
+  100004:	4e 80 00 20 	blr

src/xenia/cpu/frontend/test/bin/instr_rlwimi.map

@@ -0,0 +1 @@
+0000000000000000 t test_rlwimi