drastically reduce size of final generated code for rlwinm by adding special paths for rotations of 0, masks that discard the rotated bits and using And w/ UINT_MAX instead of truncate/zero extend

Add special case to TYPE_INT64's EmitAnd for UINT_MAX mask. Do mov32 to 32 if detected to take advantage of implicit zero xt/reg renaming

Add helper function for skipping assignment defs in instr.
Add helper function for checking if an opcode is binary value type
Add several new optimizations to simplificationpass, plus weak NZM calculation code (better full evaluation of Z/NZ will be done later) .
 List of optimizations:
  If a value is anded with a bitmask that it was already masked against, reuse the old value (this cuts out most FPSCR update garbage, although it does cause a local variable to be allocated for the masked FPSCR and it still repeatedly stores the masked value to the context)
  If masking a value that was or'ed against another check whether our mask only considers bits from one value or another. if so, change the operand to the OR input that actually matters
  If the only usage of a rotate left's output is an AND against a mask that discards the bits that were rotated in change the opcode to SHIFT_LEFT
  If masking against all ones, become an assign.
  If XOR or OR against 0, become an assign (additional FPSCR codegen cleanup)
  If XOR against all ones, become a NOT
Adding a direct CPUID check to x64_emitter for lzcnt, the version of xbyak we are using is skipping checking for lzcnt on all non-intel cpus, meaning we are generating the much slower bitscan path for AMD cpus.

src/xenia/cpu/hir/instr.cc

@@ -114,7 +114,20 @@ void Instr::Remove() {
     block->instr_tail = prev;
   }
 }
+Instr* Instr::GetDestDefSkipAssigns() {
+  Instr* current_def = this;
 
+  while (current_def->opcode == &OPCODE_ASSIGN_info) {
+    Instr* next_def = current_def->src1.value->def;
+
+    if (!next_def) {
+      return nullptr;
+    }
+
+    current_def = next_def;
+  }
+  return current_def;
+}
 }  // namespace hir
 }  // namespace cpu
 }  // namespace xe

src/xenia/cpu/hir/instr.h

@@ -59,6 +59,52 @@ class Instr {
   void MoveBefore(Instr* other);
   void Replace(const OpcodeInfo* new_opcode, uint16_t new_flags);
   void Remove();
+
+  template <typename TPredicate>
+  std::pair<Value*, Value*> BinaryValueArrangeByPredicateExclusive(
+      TPredicate&& pred) {
+    auto src1_value = src1.value;
+    auto src2_value = src2.value;
+    if (!src1_value || !src2_value) return {nullptr, nullptr};
+
+    if (!opcode) return {nullptr, nullptr};  // impossible!
+
+    // check if binary opcode taking two values. we dont care if the dest is a
+    // value
+
+    if (!IsOpcodeBinaryValue(opcode->signature)) return {nullptr, nullptr};
+
+    if (pred(src1_value)) {
+      if (pred(src2_value)) {
+        return {nullptr, nullptr};
+      } else {
+        return {src1_value, src2_value};
+      }
+    } else if (pred(src2_value)) {
+      return {src2_value, src1_value};
+    } else {
+      return {nullptr, nullptr};
+    }
+  }
+
+  /*
+if src1 is constant, and src2 is not, return [src1, src2]
+if src2 is constant, and src1 is not, return [src2, src1]
+if neither is constant, return nullptr, nullptr
+if both are constant, return nullptr, nullptr
+*/
+  std::pair<Value*, Value*> BinaryValueArrangeAsConstAndVar() {
+    return BinaryValueArrangeByPredicateExclusive(
+        [](Value* value) { return value->IsConstant(); });
+  }
+  std::pair<Value*, Value*> BinaryValueArrangeByDefiningOpcode(
+      const OpcodeInfo* op_ptr) {
+    return BinaryValueArrangeByPredicateExclusive([op_ptr](Value* value) {
+      return value->def && value->def->opcode == op_ptr;
+    });
+  }
+
+  Instr* GetDestDefSkipAssigns();
 };
 
 }  // namespace hir

src/xenia/cpu/hir/opcodes.h

@@ -347,6 +347,10 @@ enum OpcodeSignature {
 #define GET_OPCODE_SIG_TYPE_SRC1(sig) (OpcodeSignatureType)((sig >> 3) & 0x7)
 #define GET_OPCODE_SIG_TYPE_SRC2(sig) (OpcodeSignatureType)((sig >> 6) & 0x7)
 #define GET_OPCODE_SIG_TYPE_SRC3(sig) (OpcodeSignatureType)((sig >> 9) & 0x7)
+static bool IsOpcodeBinaryValue(uint32_t signature) {
+  return (signature & ~(0x7)) ==
+         ((OPCODE_SIG_TYPE_V << 3) | (OPCODE_SIG_TYPE_V << 6));
+}
 
 typedef struct {
   uint32_t flags;

src/xenia/cpu/hir/value.h

@@ -57,6 +57,15 @@ inline size_t GetTypeSize(TypeName type_name) {
       return 0;
   }
 }
+inline uint64_t GetScalarTypeMask(TypeName type_name) {
+  size_t mask_width = GetTypeSize(type_name);
+
+  if (mask_width == 8) {
+    return ~0ULL;
+  } else {
+    return (1ULL << (mask_width * CHAR_BIT)) - 1;
+  }
+}
 
 enum ValueFlags {
   VALUE_IS_CONSTANT = (1 << 1),
@@ -68,6 +77,23 @@ struct RegAssignment {
   int32_t index;
 };
 
+struct ValueMask {
+  uint64_t low;   // low 64 bits, usually for scalar values
+  uint64_t high;  // high 64 bits, only used for vector types
+
+  ValueMask(uint64_t _low, uint64_t _high) : low(_low), high(_high) {}
+
+  ValueMask operator&(ValueMask other) const {
+    return ValueMask{low & other.low, high & other.high};
+  }
+  ValueMask operator|(ValueMask other) const {
+    return ValueMask{low | other.low, high | other.high};
+  }
+  ValueMask operator^(ValueMask other) const {
+    return ValueMask{low ^ other.low, high ^ other.high};
+  }
+};
+
 class Value {
  public:
   typedef struct Use_s {