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[Testing] Add missing control instruction tests

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This commit is contained in:
Herman S.
2025-10-14 23:59:52 +09:00
parent 72f81b56c7
commit 32b0e2c323
9 changed files with 1391 additions and 0 deletions
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159
src/xenia/cpu/ppc/testing/instr_crand.s Normal file
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test_crand_1:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 3
#_ REGISTER_IN r6 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crand 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0xA8000000
test_crand_1_constant:
li r3, 1
li r4, 2
li r5, 3
li r6, 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crand 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0xA8000000
test_crand_2:
#_ REGISTER_IN r3 2
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 4
#_ REGISTER_IN r6 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crand 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x64000000
test_crand_2_constant:
li r3, 2
li r4, 1
li r5, 4
li r6, 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crand 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x64000000
test_crand_3:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
#_ REGISTER_IN r6 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crand 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x22000000
test_crand_3_constant:
li r3, 1
li r4, 1
li r5, 2
li r6, 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crand 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x22000000
test_crand_4:
#_ REGISTER_IN r3 5
#_ REGISTER_IN r4 5
#_ REGISTER_IN r5 10
#_ REGISTER_IN r6 10
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crand 10, 10, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 5
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00220000
test_crand_4_constant:
li r3, 5
li r4, 5
li r5, 10
li r6, 10
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crand 10, 10, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 5
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00220000
test_crand_5:
#_ REGISTER_IN r3 100
#_ REGISTER_IN r4 50
#_ REGISTER_IN r5 10
#_ REGISTER_IN r6 20
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crand 17, 17, 20
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00004800
test_crand_5_constant:
li r3, 100
li r4, 50
li r5, 10
li r6, 20
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crand 17, 17, 20
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00004800

159
src/xenia/cpu/ppc/testing/instr_crandc.s Normal file
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test_crandc_1:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 3
#_ REGISTER_IN r6 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crandc 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0x88000000
test_crandc_1_constant:
li r3, 1
li r4, 2
li r5, 3
li r6, 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crandc 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0x88000000
test_crandc_2:
#_ REGISTER_IN r3 2
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 4
#_ REGISTER_IN r6 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crandc 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x44000000
test_crandc_2_constant:
li r3, 2
li r4, 1
li r5, 4
li r6, 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crandc 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x44000000
test_crandc_3:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
#_ REGISTER_IN r6 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crandc 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x02000000
test_crandc_3_constant:
li r3, 1
li r4, 1
li r5, 2
li r6, 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crandc 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x02000000
test_crandc_4:
#_ REGISTER_IN r3 5
#_ REGISTER_IN r4 10
#_ REGISTER_IN r5 20
#_ REGISTER_IN r6 20
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crandc 10, 8, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 10
#_ REGISTER_OUT r5 20
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00820000
test_crandc_4_constant:
li r3, 5
li r4, 10
li r5, 20
li r6, 20
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crandc 10, 8, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 10
#_ REGISTER_OUT r5 20
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00820000
test_crandc_5:
#_ REGISTER_IN r3 100
#_ REGISTER_IN r4 100
#_ REGISTER_IN r5 50
#_ REGISTER_IN r6 25
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crandc 18, 18, 21
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 100
#_ REGISTER_OUT r5 50
#_ REGISTER_OUT r6 25
#_ REGISTER_OUT r12 0x00000400
test_crandc_5_constant:
li r3, 100
li r4, 100
li r5, 50
li r6, 25
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crandc 18, 18, 21
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 100
#_ REGISTER_OUT r5 50
#_ REGISTER_OUT r6 25
#_ REGISTER_OUT r12 0x00000400

159
src/xenia/cpu/ppc/testing/instr_creqv.s Normal file
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test_creqv_1:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 3
#_ REGISTER_IN r6 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
creqv 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0xA8000000
test_creqv_1_constant:
li r3, 1
li r4, 2
li r5, 3
li r6, 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
creqv 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0xA8000000
test_creqv_2:
#_ REGISTER_IN r3 2
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 4
#_ REGISTER_IN r6 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
creqv 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x64000000
test_creqv_2_constant:
li r3, 2
li r4, 1
li r5, 4
li r6, 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
creqv 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x64000000
test_creqv_3:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
#_ REGISTER_IN r6 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
creqv 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x22000000
test_creqv_3_constant:
li r3, 1
li r4, 1
li r5, 2
li r6, 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
creqv 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x22000000
test_creqv_4:
#_ REGISTER_IN r3 5
#_ REGISTER_IN r4 5
#_ REGISTER_IN r5 10
#_ REGISTER_IN r6 10
cmpw cr2, r3, r4
cmpw cr3, r5, r6
creqv 10, 10, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_IN r4 5
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00220000
test_creqv_4_constant:
li r3, 5
li r4, 5
li r5, 10
li r6, 10
cmpw cr2, r3, r4
cmpw cr3, r5, r6
creqv 10, 10, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 5
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00220000
test_creqv_5:
#_ REGISTER_IN r3 100
#_ REGISTER_IN r4 50
#_ REGISTER_IN r5 25
#_ REGISTER_IN r6 25
cmpw cr4, r3, r4
cmpw cr5, r5, r6
creqv 17, 17, 22
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 25
#_ REGISTER_OUT r6 25
#_ REGISTER_OUT r12 0x00004200
test_creqv_5_constant:
li r3, 100
li r4, 50
li r5, 25
li r6, 25
cmpw cr4, r3, r4
cmpw cr5, r5, r6
creqv 17, 17, 22
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 25
#_ REGISTER_OUT r6 25
#_ REGISTER_OUT r12 0x00004200

159
src/xenia/cpu/ppc/testing/instr_crnand.s Normal file
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test_crnand_1:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 3
#_ REGISTER_IN r6 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnand 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0x88000000
test_crnand_1_constant:
li r3, 1
li r4, 2
li r5, 3
li r6, 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnand 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0x88000000
test_crnand_2:
#_ REGISTER_IN r3 2
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 4
#_ REGISTER_IN r6 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnand 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x44000000
test_crnand_2_constant:
li r3, 2
li r4, 1
li r5, 4
li r6, 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnand 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x44000000
test_crnand_3:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
#_ REGISTER_IN r6 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnand 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x02000000
test_crnand_3_constant:
li r3, 1
li r4, 1
li r5, 2
li r6, 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnand 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x02000000
test_crnand_4:
#_ REGISTER_IN r3 5
#_ REGISTER_IN r4 5
#_ REGISTER_IN r5 10
#_ REGISTER_IN r6 10
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crnand 10, 10, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 5
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00020000
test_crnand_4_constant:
li r3, 5
li r4, 5
li r5, 10
li r6, 10
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crnand 10, 10, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 5
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00020000
test_crnand_5:
#_ REGISTER_IN r3 100
#_ REGISTER_IN r4 50
#_ REGISTER_IN r5 10
#_ REGISTER_IN r6 20
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crnand 17, 17, 20
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00000800
test_crnand_5_constant:
li r3, 100
li r4, 50
li r5, 10
li r6, 20
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crnand 17, 17, 20
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00000800

159
src/xenia/cpu/ppc/testing/instr_crnor.s Normal file
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test_crnor_1:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 3
#_ REGISTER_IN r6 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnor 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0x88000000
test_crnor_1_constant:
li r3, 1
li r4, 2
li r5, 3
li r6, 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnor 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0x88000000
test_crnor_2:
#_ REGISTER_IN r3 2
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 4
#_ REGISTER_IN r6 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnor 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x44000000
test_crnor_2_constant:
li r3, 2
li r4, 1
li r5, 4
li r6, 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnor 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x44000000
test_crnor_3:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
#_ REGISTER_IN r6 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnor 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x02000000
test_crnor_3_constant:
li r3, 1
li r4, 1
li r5, 2
li r6, 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crnor 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x02000000
test_crnor_4:
#_ REGISTER_IN r3 5
#_ REGISTER_IN r4 10
#_ REGISTER_IN r5 15
#_ REGISTER_IN r6 20
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crnor 10, 8, 12
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 10
#_ REGISTER_OUT r5 15
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00880000
test_crnor_4_constant:
li r3, 5
li r4, 10
li r5, 15
li r6, 20
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crnor 10, 8, 12
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 10
#_ REGISTER_OUT r5 15
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00880000
test_crnor_5:
#_ REGISTER_IN r3 100
#_ REGISTER_IN r4 50
#_ REGISTER_IN r5 10
#_ REGISTER_IN r6 10
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crnor 17, 17, 22
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00000200
test_crnor_5_constant:
li r3, 100
li r4, 50
li r5, 10
li r6, 10
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crnor 17, 17, 22
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00000200

159
src/xenia/cpu/ppc/testing/instr_cror.s Normal file
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test_cror_1:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 3
#_ REGISTER_IN r6 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
cror 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0xA8000000
test_cror_1_constant:
li r3, 1
li r4, 2
li r5, 3
li r6, 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
cror 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0xA8000000
test_cror_2:
#_ REGISTER_IN r3 2
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 4
#_ REGISTER_IN r6 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
cror 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x64000000
test_cror_2_constant:
li r3, 2
li r4, 1
li r5, 4
li r6, 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
cror 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x64000000
test_cror_3:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
#_ REGISTER_IN r6 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
cror 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x22000000
test_cror_3_constant:
li r3, 1
li r4, 1
li r5, 2
li r6, 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
cror 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x22000000
test_cror_4:
#_ REGISTER_IN r3 5
#_ REGISTER_IN r4 10
#_ REGISTER_IN r5 15
#_ REGISTER_IN r6 20
cmpw cr2, r3, r4
cmpw cr3, r5, r6
cror 10, 8, 12
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 10
#_ REGISTER_OUT r5 15
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00A80000
test_cror_4_constant:
li r3, 5
li r4, 10
li r5, 15
li r6, 20
cmpw cr2, r3, r4
cmpw cr3, r5, r6
cror 10, 8, 12
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 10
#_ REGISTER_OUT r5 15
#_ REGISTER_OUT r6 20
#_ REGISTER_OUT r12 0x00A80000
test_cror_5:
#_ REGISTER_IN r3 100
#_ REGISTER_IN r4 50
#_ REGISTER_IN r5 10
#_ REGISTER_IN r6 10
cmpw cr4, r3, r4
cmpw cr5, r5, r6
cror 17, 17, 22
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00004200
test_cror_5_constant:
li r3, 100
li r4, 50
li r5, 10
li r6, 10
cmpw cr4, r3, r4
cmpw cr5, r5, r6
cror 17, 17, 22
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00004200

159
src/xenia/cpu/ppc/testing/instr_crorc.s Normal file
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test_crorc_1:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 3
#_ REGISTER_IN r6 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crorc 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0xA8000000
test_crorc_1_constant:
li r3, 1
li r4, 2
li r5, 3
li r6, 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crorc 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0xA8000000
test_crorc_2:
#_ REGISTER_IN r3 2
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 4
#_ REGISTER_IN r6 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crorc 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x64000000
test_crorc_2_constant:
li r3, 2
li r4, 1
li r5, 4
li r6, 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crorc 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x64000000
test_crorc_3:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
#_ REGISTER_IN r6 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crorc 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x22000000
test_crorc_3_constant:
li r3, 1
li r4, 1
li r5, 2
li r6, 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crorc 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x22000000
test_crorc_4:
#_ REGISTER_IN r3 5
#_ REGISTER_IN r4 10
#_ REGISTER_IN r5 15
#_ REGISTER_IN r6 15
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crorc 10, 8, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 10
#_ REGISTER_OUT r5 15
#_ REGISTER_OUT r6 15
#_ REGISTER_OUT r12 0x00A20000
test_crorc_4_constant:
li r3, 5
li r4, 10
li r5, 15
li r6, 15
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crorc 10, 8, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 10
#_ REGISTER_OUT r5 15
#_ REGISTER_OUT r6 15
#_ REGISTER_OUT r12 0x00A20000
test_crorc_5:
#_ REGISTER_IN r3 100
#_ REGISTER_IN r4 100
#_ REGISTER_IN r5 50
#_ REGISTER_IN r6 25
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crorc 18, 18, 21
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 100
#_ REGISTER_OUT r5 50
#_ REGISTER_OUT r6 25
#_ REGISTER_OUT r12 0x00002400
test_crorc_5_constant:
li r3, 100
li r4, 100
li r5, 50
li r6, 25
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crorc 18, 18, 21
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 100
#_ REGISTER_OUT r5 50
#_ REGISTER_OUT r6 25
#_ REGISTER_OUT r12 0x00002400

159
src/xenia/cpu/ppc/testing/instr_crxor.s Normal file
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test_crxor_1:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 3
#_ REGISTER_IN r6 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crxor 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0x88000000
test_crxor_1_constant:
li r3, 1
li r4, 2
li r5, 3
li r6, 4
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crxor 2, 0, 4
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 3
#_ REGISTER_OUT r6 4
#_ REGISTER_OUT r12 0x88000000
test_crxor_2:
#_ REGISTER_IN r3 2
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 4
#_ REGISTER_IN r6 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crxor 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x44000000
test_crxor_2_constant:
li r3, 2
li r4, 1
li r5, 4
li r6, 3
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crxor 2, 1, 5
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 4
#_ REGISTER_OUT r6 3
#_ REGISTER_OUT r12 0x44000000
test_crxor_3:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
#_ REGISTER_IN r6 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crxor 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x02000000
test_crxor_3_constant:
li r3, 1
li r4, 1
li r5, 2
li r6, 2
cmpw cr0, r3, r4
cmpw cr1, r5, r6
crxor 2, 2, 6
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 2
#_ REGISTER_OUT r12 0x02000000
test_crxor_4:
#_ REGISTER_IN r3 5
#_ REGISTER_IN r4 5
#_ REGISTER_IN r5 10
#_ REGISTER_IN r6 10
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crxor 10, 10, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 5
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00020000
test_crxor_4_constant:
li r3, 5
li r4, 5
li r5, 10
li r6, 10
cmpw cr2, r3, r4
cmpw cr3, r5, r6
crxor 10, 10, 14
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 5
#_ REGISTER_OUT r5 10
#_ REGISTER_OUT r6 10
#_ REGISTER_OUT r12 0x00020000
test_crxor_5:
#_ REGISTER_IN r3 100
#_ REGISTER_IN r4 50
#_ REGISTER_IN r5 25
#_ REGISTER_IN r6 25
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crxor 17, 17, 22
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 25
#_ REGISTER_OUT r6 25
#_ REGISTER_OUT r12 0x00000200
test_crxor_5_constant:
li r3, 100
li r4, 50
li r5, 25
li r6, 25
cmpw cr4, r3, r4
cmpw cr5, r5, r6
crxor 17, 17, 22
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r5 25
#_ REGISTER_OUT r6 25
#_ REGISTER_OUT r12 0x00000200

119
src/xenia/cpu/ppc/testing/instr_mcrf.s Normal file
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test_mcrf_1:
#_ REGISTER_IN r3 1
#_ REGISTER_IN r4 2
cmpw cr0, r3, r4
mcrf cr1, cr0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r12 0x88000000
test_mcrf_1_constant:
li r3, 1
li r4, 2
cmpw cr0, r3, r4
mcrf cr1, cr0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r12 0x88000000
test_mcrf_2:
#_ REGISTER_IN r3 2
#_ REGISTER_IN r4 1
cmpw cr0, r3, r4
mcrf cr2, cr0
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r12 0x40400000
test_mcrf_2_constant:
li r3, 2
li r4, 1
cmpw cr0, r3, r4
mcrf cr2, cr0
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r12 0x40400000
test_mcrf_3:
#_ REGISTER_IN r3 5
#_ REGISTER_IN r4 5
cmpw cr3, r3, r4
mcrf cr0, cr3
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 5
#_ REGISTER_OUT r12 0x40020000
test_mcrf_3_constant:
li r3, 5
li r4, 5
cmpw cr3, r3, r4
mcrf cr0, cr3
mfcr r12
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 5
#_ REGISTER_OUT r12 0x40020000
test_mcrf_4:
#_ REGISTER_IN r3 100
#_ REGISTER_IN r4 50
cmpw cr5, r3, r4
mcrf cr7, cr5
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r12 0x00000404
test_mcrf_4_constant:
li r3, 100
li r4, 50
cmpw cr5, r3, r4
mcrf cr7, cr5
mfcr r12
blr
#_ REGISTER_OUT r3 100
#_ REGISTER_OUT r4 50
#_ REGISTER_OUT r12 0x00000404
test_mcrf_5:
#_ REGISTER_IN r3 10
#_ REGISTER_IN r4 20
#_ REGISTER_IN r5 30
#_ REGISTER_IN r6 30
cmpw cr2, r3, r4
cmpw cr4, r5, r6
mcrf cr6, cr2
mfcr r12
blr
#_ REGISTER_OUT r3 10
#_ REGISTER_OUT r4 20
#_ REGISTER_OUT r5 30
#_ REGISTER_OUT r6 30
#_ REGISTER_OUT r12 0x00802040
test_mcrf_5_constant:
li r3, 10
li r4, 20
li r5, 30
li r6, 30
cmpw cr2, r3, r4
cmpw cr4, r5, r6
mcrf cr6, cr2
mfcr r12
blr
#_ REGISTER_OUT r3 10
#_ REGISTER_OUT r4 20
#_ REGISTER_OUT r5 30
#_ REGISTER_OUT r6 30
#_ REGISTER_OUT r12 0x00802040