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Tests for vpkd3d128 d3dcolor.

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This commit is contained in:
Ben Vanik
2014-11-02 17:32:50 -08:00
parent 9cb4fe03a4
commit 32f42cd5ae
4 changed files with 210 additions and 0 deletions
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135
src/alloy/frontend/ppc/test/instr_vpkd3d128.s Normal file
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# vpkd3d128 dest, src, type, mask, shift
# type:
# 0 = PACK_TYPE_D3DCOLOR
# 1 = PACK_TYPE_SHORT_2
# 3 = PACK_TYPE_FLOAT16_2
# 5 = PACK_TYPE_FLOAT16_4
# mask:
# must not be zero
# 1 = 00000000 00000000 00000000 FFFFFFFF
# 2 = 00000000 00000000 FFFFFFFF FFFFFFFF
# 3 = same as 2? except mask3/shift3
# shift:
# 0 = no shift
# 1 = shift left by one word
# 2 ...
# 3 ...
# special case: mask3/shift3 = 00000000 00000000 00000000 FFFFFFFF
# vpkd3d128 is broken in binutils, so these are hand coded
test_vpkd3d128_d3dcolor_invalid_0:
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 0
.long 0x18811E10
blr
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
test_vpkd3d128_d3dcolor_invalid_1:
#_ REGISTER_IN v3 [40800000, 40000000, C2F60000, 4B3BDF83]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 0
.long 0x18811E10
blr
#_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, 4B3BDF83]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF0000]
test_vpkd3d128_d3dcolor_1_0:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 0
.long 0x18811E10
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vpkd3d128_d3dcolor_1_1:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 1
.long 0x18811E50
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 04010203, CDCDCDCD]
test_vpkd3d128_d3dcolor_1_2:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 2
.long 0x18811E90
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, 04010203, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_1_3:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 3
.long 0x18811ED0
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_2_0:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 2, 0
.long 0x18821E10
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
test_vpkd3d128_d3dcolor_2_1:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 2, 1
.long 0x18821E50
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
test_vpkd3d128_d3dcolor_2_2:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 2, 2
.long 0x18821E90
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_2_3:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 2, 3
.long 0x18821ED0
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_3_0:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 3, 0
.long 0x18831E10
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
test_vpkd3d128_d3dcolor_3_1:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 3, 1
.long 0x18831E50
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
test_vpkd3d128_d3dcolor_3_2:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 3, 2
.long 0x18831E90
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_3_3:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 3, 3
.long 0x18831ED0
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]