fabi/Xenia-Canary
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge pull request #64 from beeanyew/cpu-updates-raiden-fighters

Browse Source 
Some minor CPU updates
This commit is contained in:
Radosław Gliński
2022-08-28 20:52:42 +02:00
committed by GitHub
parent 04c9c02270 3569e97e0e
commit 335a390d43
1 changed files with 40 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

74
src/xenia/cpu/ppc/ppc_emit_alu.cc
View File

@@ -87,15 +87,16 @@ int InstrEmit_addex(PPCHIRBuilder& f, const InstrData& i) {
Value* rb = f.LoadGPR(i.XO.RB); Value* rb = f.LoadGPR(i.XO.RB);
Value* v = f.AddWithCarry(ra, rb, f.LoadCA()); Value* v = f.AddWithCarry(ra, rb, f.LoadCA());
f.StoreGPR(i.XO.RT, v); f.StoreGPR(i.XO.RT, v);
if (i.XO.OE) { f.StoreCA(AddWithCarryDidCarry(f, ra, rb, f.LoadCA()));
XEINSTRNOTIMPLEMENTED();
// e.update_xer_with_overflow(EFLAGS OF?);
} else {
f.StoreCA(AddWithCarryDidCarry(f, ra, rb, f.LoadCA()));
}
if (i.XO.Rc) { if (i.XO.Rc) {
f.UpdateCR(0, v); f.UpdateCR(0, v);
} }
if (i.XO.OE) {
// Stub implementation.
// TODO: Handle overflow flag.
// NOTE: 535507D4 (Raiden Fighters Aces) never seems to rely on this
// behavior either, despite OE being set.
}
return 0; return 0;
} }
@@ -416,34 +417,21 @@ int InstrEmit_mullwx(PPCHIRBuilder& f, const InstrData& i) {
int InstrEmit_negx(PPCHIRBuilder& f, const InstrData& i) { int InstrEmit_negx(PPCHIRBuilder& f, const InstrData& i) {
// RT <- ¬(RA) + 1 // RT <- ¬(RA) + 1
if (i.XO.OE) { if (i.XO.OE) {
// With XER update. // Stub implementation.
// This is a different codepath as we need to use llvm.ssub.with.overflow. // TODO: Handle overflow flag for XER.
// NOTE: 535507D4 (Raiden Fighters Aces) never seems to rely on this
// if RA == 0x8000000000000000 then no-op and set OV=1 // behavior, despite having OE set.
// This may just magically do that... Value* v = f.LoadGPR(i.XO.RA);
if (v->AsUint64() == 0x8000000000000000) {
XEINSTRNOTIMPLEMENTED(); f.StoreGPR(i.XO.RT, v);
return 1; return 0;
// Function* ssub_with_overflow = Intrinsic::getDeclaration(
// e.gen_module(), Intrinsic::ssub_with_overflow, jit_type_nint);
// jit_value_t v = b.CreateCall2(ssub_with_overflow,
// e.get_int64(0), f.LoadGPR(i.XO.RA));
// jit_value_t v0 = b.CreateExtractValue(v, 0);
// f.StoreGPR(i.XO.RT, v0);
// e.update_xer_with_overflow(b.CreateExtractValue(v, 1));
// if (i.XO.Rc) {
// // With cr0 update.
// f.UpdateCR(0, v0, e.get_int64(0), true);
//}
} else {
// No OE bit setting.
Value* v = f.Neg(f.LoadGPR(i.XO.RA));
f.StoreGPR(i.XO.RT, v);
if (i.XO.Rc) {
f.UpdateCR(0, v);
} }
} }
Value* v = f.Neg(f.LoadGPR(i.XO.RA));
f.StoreGPR(i.XO.RT, v);
if (i.XO.Rc) {
f.UpdateCR(0, v);
}
return 0; return 0;
} }
@@ -925,8 +913,26 @@ int InstrEmit_rldcrx(PPCHIRBuilder& f, const InstrData& i) {
} }
int InstrEmit_rldicx(PPCHIRBuilder& f, const InstrData& i) { int InstrEmit_rldicx(PPCHIRBuilder& f, const InstrData& i) {
XEINSTRNOTIMPLEMENTED(); // n <- sh[5] || sh[0:4]
return 1; // r <- ROTL64(RS, n)
// b <- mb[5] || mb[0:4]
// m <- MASK(b, ~n)
// RA <- r & m
// TODO: Check if this makes any sense. It works in 535507D4,
// but it's the only title I could find that uses this instruction.
uint32_t sh = (i.MD.SH5 << 5) | i.MD.SH;
uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB;
uint64_t m = XEMASK(mb, ~sh);
Value* v = f.LoadGPR(i.MD.RT);
if (sh) {
v = f.RotateLeft(v, f.LoadConstantInt8(sh));
}
v = f.And(v, f.LoadConstantUint64(m));
f.StoreGPR(i.MD.RA, v);
if (i.MD.Rc) {
f.UpdateCR(0, v);
}
return 0;
} }
int InstrEmit_rldiclx(PPCHIRBuilder& f, const InstrData& i) { int InstrEmit_rldiclx(PPCHIRBuilder& f, const InstrData& i) {