vsl[bhw] tests.

src/alloy/frontend/ppc/test/bin/instr_vslb.dis

@@ -0,0 +1,25 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslb.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vslb_1>:
+  100000:	10 63 21 04 	vslb    v3,v3,v4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vslb_2>:
+  100008:	10 63 21 04 	vslb    v3,v3,v4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vslb_3>:
+  100010:	10 63 21 04 	vslb    v3,v3,v4
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vslb_4>:
+  100018:	10 63 21 04 	vslb    v3,v3,v4
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_vslb_5>:
+  100020:	10 63 21 04 	vslb    v3,v3,v4
+  100024:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vslb.map

@@ -0,0 +1,5 @@
+0000000000000000 t test_vslb_1
+0000000000000008 t test_vslb_2
+0000000000000010 t test_vslb_3
+0000000000000018 t test_vslb_4
+0000000000000020 t test_vslb_5

src/alloy/frontend/ppc/test/bin/instr_vslh.dis

@@ -0,0 +1,29 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslh.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vslh_1>:
+  100000:	10 63 21 44 	vslh    v3,v3,v4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vslh_2>:
+  100008:	10 63 21 44 	vslh    v3,v3,v4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vslh_3>:
+  100010:	10 63 21 44 	vslh    v3,v3,v4
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vslh_4>:
+  100018:	10 63 21 44 	vslh    v3,v3,v4
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_vslh_5>:
+  100020:	10 63 21 44 	vslh    v3,v3,v4
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_vslh_6>:
+  100028:	10 63 21 44 	vslh    v3,v3,v4
+  10002c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vslh.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_vslh_1
+0000000000000008 t test_vslh_2
+0000000000000010 t test_vslh_3
+0000000000000018 t test_vslh_4
+0000000000000020 t test_vslh_5
+0000000000000028 t test_vslh_6

src/alloy/frontend/ppc/test/bin/instr_vslw.dis

@@ -0,0 +1,29 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vslw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vslw_1>:
+  100000:	10 63 21 84 	vslw    v3,v3,v4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vslw_2>:
+  100008:	10 63 21 84 	vslw    v3,v3,v4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vslw_3>:
+  100010:	10 63 21 84 	vslw    v3,v3,v4
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vslw_4>:
+  100018:	10 63 21 84 	vslw    v3,v3,v4
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_vslw_5>:
+  100020:	10 63 21 84 	vslw    v3,v3,v4
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_vslw_6>:
+  100028:	10 63 21 84 	vslw    v3,v3,v4
+  10002c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vslw.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_vslw_1
+0000000000000008 t test_vslw_2
+0000000000000010 t test_vslw_3
+0000000000000018 t test_vslw_4
+0000000000000020 t test_vslw_5
+0000000000000028 t test_vslw_6