[Testing] add missing saturate arithmetic tests

src/xenia/cpu/ppc/testing/instr_vaddsbs.s

@@ -0,0 +1,71 @@
+test_vaddsbs_1:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [02020202, 02020202, 02020202, 02020202]
+
+test_vaddsbs_2:
+  #_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+
+test_vaddsbs_3:
+  #_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_IN v4 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  vaddsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_OUT v4 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_OUT v5 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+
+test_vaddsbs_4:
+  #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vaddsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [80808080, 80808080, 80808080, 80808080]
+
+test_vaddsbs_5:
+  #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_IN v4 [80808080, 80808080, 80808080, 80808080]
+  vaddsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_OUT v4 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_OUT v5 [80808080, 80808080, 80808080, 80808080]
+
+test_vaddsbs_6:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vaddsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vaddsbs_7:
+  #_ REGISTER_IN v3 [7E7E7E7E, 7E7E7E7E, 7E7E7E7E, 7E7E7E7E]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7E7E7E7E, 7E7E7E7E, 7E7E7E7E, 7E7E7E7E]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+
+test_vaddsbs_8:
+  #_ REGISTER_IN v3 [7E7E7E7E, FEFEFEFE, 01020304, 05060708]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7E7E7E7E, FEFEFEFE, 01020304, 05060708]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [7F7F7F7F, FFFFFFFF, 02030405, 06070809]

src/xenia/cpu/ppc/testing/instr_vaddshs.s

@@ -5,3 +5,39 @@ test_vaddshs_1:
   blr
   #_ REGISTER_OUT v3 [7fff8000, 7fff8003, 7fff8000, 80068007]
   #_ REGISTER_OUT v4 [00018001, 10000000, 42568124, 00000000]
+
+test_vaddshs_2:
+  #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vaddshs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00020002, 00020002, 00020002, 00020002]
+
+test_vaddshs_3:
+  #_ REGISTER_IN v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_IN v4 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  vaddshs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_OUT v4 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_OUT v5 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+
+test_vaddshs_4:
+  #_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_IN v4 [80008000, 80008000, 80008000, 80008000]
+  vaddshs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_OUT v4 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_OUT v5 [80008000, 80008000, 80008000, 80008000]
+
+test_vaddshs_5:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vaddshs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]

src/xenia/cpu/ppc/testing/instr_vaddsws.s

@@ -0,0 +1,53 @@
+test_vaddsws_1:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vaddsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000002, 00000002, 00000002, 00000002]
+
+test_vaddsws_2:
+  #_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vaddsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+
+test_vaddsws_3:
+  #_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_IN v4 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  vaddsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_OUT v4 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_OUT v5 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+
+test_vaddsws_4:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vaddsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
+
+test_vaddsws_5:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [80000000, 80000000, 80000000, 80000000]
+  vaddsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_OUT v4 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
+
+test_vaddsws_6:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vaddsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]

src/xenia/cpu/ppc/testing/instr_vaddubs.s

@@ -0,0 +1,53 @@
+test_vaddubs_1:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddubs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [02020202, 02020202, 02020202, 02020202]
+
+test_vaddubs_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddubs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vaddubs_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vaddubs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vaddubs_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vaddubs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vaddubs_5:
+  #_ REGISTER_IN v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddubs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vaddubs_6:
+  #_ REGISTER_IN v3 [80402010, 08040201, 01020408, 10204080]
+  #_ REGISTER_IN v4 [01010101, 01010101, FF0F0F0F, 01010101]
+  vaddubs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80402010, 08040201, 01020408, 10204080]
+  #_ REGISTER_OUT v4 [01010101, 01010101, FF0F0F0F, 01010101]
+  #_ REGISTER_OUT v5 [81412111, 09050302, FF111317, 11214181]

src/xenia/cpu/ppc/testing/instr_vadduhs.s

@@ -0,0 +1,53 @@
+test_vadduhs_1:
+  #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vadduhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00020002, 00020002, 00020002, 00020002]
+
+test_vadduhs_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vadduhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vadduhs_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vadduhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vadduhs_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vadduhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vadduhs_5:
+  #_ REGISTER_IN v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vadduhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vadduhs_6:
+  #_ REGISTER_IN v3 [80004000, 20001000, 01000200, 04000800]
+  #_ REGISTER_IN v4 [00010001, 00010001, FFFF0FFF, 00010001]
+  vadduhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80004000, 20001000, 01000200, 04000800]
+  #_ REGISTER_OUT v4 [00010001, 00010001, FFFF0FFF, 00010001]
+  #_ REGISTER_OUT v5 [80014001, 20011001, FFFF11FF, 04010801]

src/xenia/cpu/ppc/testing/instr_vadduws.s

@@ -0,0 +1,53 @@
+test_vadduws_1:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vadduws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000002, 00000002, 00000002, 00000002]
+
+test_vadduws_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vadduws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vadduws_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vadduws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vadduws_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vadduws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vadduws_5:
+  #_ REGISTER_IN v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vadduws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vadduws_6:
+  #_ REGISTER_IN v3 [80000000, 40000000, 20000000, 10000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, FFFFFFFF, 00000001]
+  vadduws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 40000000, 20000000, 10000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, FFFFFFFF, 00000001]
+  #_ REGISTER_OUT v5 [80000001, 40000001, FFFFFFFF, 10000001]

src/xenia/cpu/ppc/testing/instr_vsubsbs.s

@@ -0,0 +1,62 @@
+test_vsubsbs_1:
+  #_ REGISTER_IN v3 [02020202, 02020202, 02020202, 02020202]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsubsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
+
+test_vsubsbs_2:
+  #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsubsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [80808080, 80808080, 80808080, 80808080]
+
+test_vsubsbs_3:
+  #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_IN v4 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  vsubsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_OUT v4 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_OUT v5 [80808080, 80808080, 80808080, 80808080]
+
+test_vsubsbs_4:
+  #_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vsubsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+
+test_vsubsbs_5:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsubsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsubsbs_6:
+  #_ REGISTER_IN v3 [81818181, 81818181, 81818181, 81818181]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsubsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [81818181, 81818181, 81818181, 81818181]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [80808080, 80808080, 80808080, 80808080]
+
+test_vsubsbs_7:
+  #_ REGISTER_IN v3 [40204060, 81827F7E, 01020304, FEFDFCFB]
+  #_ REGISTER_IN v4 [01010101, 01010101, 7F7F7F7F, 01010101]
+  vsubsbs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [40204060, 81827F7E, 01020304, FEFDFCFB]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 7F7F7F7F, 01010101]
+  #_ REGISTER_OUT v5 [3F1F3F5F, 80817E7D, 82838485, FDFCFBFA]

src/xenia/cpu/ppc/testing/instr_vsubshs.s

@@ -13,3 +13,30 @@ test_vsubshs_2:
   blr
   #_ REGISTER_OUT v3 [7FFF8000, 6FFF8003, 3DA9FEE1, 80068007]
   #_ REGISTER_OUT v4 [FFFF0005, 10000000, 42568124, 00000000]
+
+test_vsubshs_3:
+  #_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vsubshs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [80008000, 80008000, 80008000, 80008000]
+
+test_vsubshs_4:
+  #_ REGISTER_IN v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vsubshs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+
+test_vsubshs_5:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsubshs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]

src/xenia/cpu/ppc/testing/instr_vsubsws.s

@@ -0,0 +1,53 @@
+test_vsubsws_1:
+  #_ REGISTER_IN v3 [00000002, 00000002, 00000002, 00000002]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
+
+test_vsubsws_2:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
+
+test_vsubsws_3:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  vsubsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_OUT v4 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
+
+test_vsubsws_4:
+  #_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vsubsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+
+test_vsubsws_5:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsubsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsubsws_6:
+  #_ REGISTER_IN v3 [80000001, 80000001, 80000001, 80000001]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubsws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000001, 80000001, 80000001, 80000001]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]

src/xenia/cpu/ppc/testing/instr_vsububs.s

@@ -0,0 +1,53 @@
+test_vsububs_1:
+  #_ REGISTER_IN v3 [02020202, 02020202, 02020202, 02020202]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsububs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
+
+test_vsububs_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsububs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsububs_3:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vsububs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsububs_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsububs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vsububs_5:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsububs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsububs_6:
+  #_ REGISTER_IN v3 [80402010, 08040201, FF0F0F0F, 10204080]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsububs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80402010, 08040201, FF0F0F0F, 10204080]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [7F3F1F0F, 07030100, FE0E0E0E, 0F1F3F7F]

src/xenia/cpu/ppc/testing/instr_vsubuhs.s

@@ -0,0 +1,53 @@
+test_vsubuhs_1:
+  #_ REGISTER_IN v3 [00020002, 00020002, 00020002, 00020002]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vsubuhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00020002, 00020002, 00020002, 00020002]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001]
+
+test_vsubuhs_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vsubuhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsubuhs_3:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vsubuhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsubuhs_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsubuhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vsubuhs_5:
+  #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vsubuhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsubuhs_6:
+  #_ REGISTER_IN v3 [80004000, 20001000, FFFF0FFF, 10000800]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vsubuhs v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80004000, 20001000, FFFF0FFF, 10000800]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [7FFF3FFF, 1FFF0FFF, FFFE0FFE, 0FFF07FF]

src/xenia/cpu/ppc/testing/instr_vsubuws.s

@@ -0,0 +1,53 @@
+test_vsubuws_1:
+  #_ REGISTER_IN v3 [00000002, 00000002, 00000002, 00000002]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubuws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
+
+test_vsubuws_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubuws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsubuws_3:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vsubuws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsubuws_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsubuws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vsubuws_5:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubuws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsubuws_6:
+  #_ REGISTER_IN v3 [80000000, 40000000, FFFFFFFF, 10000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubuws v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 40000000, FFFFFFFF, 10000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [7FFFFFFF, 3FFFFFFF, FFFFFFFE, 0FFFFFFF]