[GPU] Remove register reinterpret_casts + WAIT_REG_MEM volatility
Hopefully prevents some potential #1971-like situations. WAIT_REG_MEM's implementation also allowed the compiler to load the value only once, which caused an infinite loop with the other changes in the commit (even in debug builds), so it's now accessed as volatile. Possibly it would be even better to replace it with some (acquire/release?) atomic load/store some day at least for the registers actually seen as participating in those waits. Also fixes the endianness being handled only on the first wait iteration in WAIT_REG_MEM.
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@@ -2486,8 +2486,8 @@ bool VulkanCommandProcessor::IssueDraw(xenos::PrimitiveType prim_type,
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(uint64_t(1) << (vfetch_index & 63))) {
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continue;
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}
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const auto& vfetch_constant = regs.Get<xenos::xe_gpu_vertex_fetch_t>(
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XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0 + vfetch_index * 2);
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xenos::xe_gpu_vertex_fetch_t vfetch_constant =
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regs.GetVertexFetch(vfetch_index);
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switch (vfetch_constant.type) {
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case xenos::FetchConstantType::kVertex:
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break;
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@@ -3285,10 +3285,10 @@ void VulkanCommandProcessor::UpdateDynamicState(
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// Blend constants.
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float blend_constants[] = {
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regs[XE_GPU_REG_RB_BLEND_RED].f32,
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regs[XE_GPU_REG_RB_BLEND_GREEN].f32,
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regs[XE_GPU_REG_RB_BLEND_BLUE].f32,
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regs[XE_GPU_REG_RB_BLEND_ALPHA].f32,
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regs.Get<float>(XE_GPU_REG_RB_BLEND_RED),
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regs.Get<float>(XE_GPU_REG_RB_BLEND_GREEN),
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regs.Get<float>(XE_GPU_REG_RB_BLEND_BLUE),
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regs.Get<float>(XE_GPU_REG_RB_BLEND_ALPHA),
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};
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dynamic_blend_constants_update_needed_ |=
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std::memcmp(dynamic_blend_constants_, blend_constants,
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@@ -3434,7 +3434,7 @@ void VulkanCommandProcessor::UpdateSystemConstantValues(
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const RegisterFile& regs = *register_file_;
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auto pa_cl_vte_cntl = regs.Get<reg::PA_CL_VTE_CNTL>();
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auto pa_su_sc_mode_cntl = regs.Get<reg::PA_SU_SC_MODE_CNTL>();
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float rb_alpha_ref = regs[XE_GPU_REG_RB_ALPHA_REF].f32;
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auto rb_alpha_ref = regs.Get<float>(XE_GPU_REG_RB_ALPHA_REF);
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auto rb_colorcontrol = regs.Get<reg::RB_COLORCONTROL>();
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auto rb_depth_info = regs.Get<reg::RB_DEPTH_INFO>();
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auto rb_stencilrefmask = regs.Get<reg::RB_STENCILREFMASK>();
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@@ -3442,7 +3442,7 @@ void VulkanCommandProcessor::UpdateSystemConstantValues(
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regs.Get<reg::RB_STENCILREFMASK>(XE_GPU_REG_RB_STENCILREFMASK_BF);
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auto rb_surface_info = regs.Get<reg::RB_SURFACE_INFO>();
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auto vgt_draw_initiator = regs.Get<reg::VGT_DRAW_INITIATOR>();
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int32_t vgt_indx_offset = int32_t(regs[XE_GPU_REG_VGT_INDX_OFFSET].u32);
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auto vgt_indx_offset = regs.Get<int32_t>(XE_GPU_REG_VGT_INDX_OFFSET);
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bool edram_fragment_shader_interlock =
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render_target_cache_->GetPath() ==
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@@ -3755,7 +3755,7 @@ void VulkanCommandProcessor::UpdateSystemConstantValues(
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dirty |= system_constants_.edram_rt_format_flags[i] != format_flags;
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system_constants_.edram_rt_format_flags[i] = format_flags;
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uint32_t blend_factors_ops =
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regs[reg::RB_BLENDCONTROL::rt_register_indices[i]].u32 & 0x1FFF1FFF;
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regs[reg::RB_BLENDCONTROL::rt_register_indices[i]] & 0x1FFF1FFF;
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dirty |= system_constants_.edram_rt_blend_factors_ops[i] !=
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blend_factors_ops;
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system_constants_.edram_rt_blend_factors_ops[i] = blend_factors_ops;
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@@ -3784,22 +3784,22 @@ void VulkanCommandProcessor::UpdateSystemConstantValues(
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if (primitive_polygonal) {
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if (pa_su_sc_mode_cntl.poly_offset_front_enable) {
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poly_offset_front_scale =
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regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE].f32;
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regs.Get<float>(XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE);
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poly_offset_front_offset =
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regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET].f32;
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regs.Get<float>(XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET);
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}
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if (pa_su_sc_mode_cntl.poly_offset_back_enable) {
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poly_offset_back_scale =
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regs[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_SCALE].f32;
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regs.Get<float>(XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_SCALE);
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poly_offset_back_offset =
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regs[XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_OFFSET].f32;
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regs.Get<float>(XE_GPU_REG_PA_SU_POLY_OFFSET_BACK_OFFSET);
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}
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} else {
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if (pa_su_sc_mode_cntl.poly_offset_para_enable) {
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poly_offset_front_scale =
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regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE].f32;
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regs.Get<float>(XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_SCALE);
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poly_offset_front_offset =
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regs[XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET].f32;
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regs.Get<float>(XE_GPU_REG_PA_SU_POLY_OFFSET_FRONT_OFFSET);
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poly_offset_back_scale = poly_offset_front_scale;
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poly_offset_back_offset = poly_offset_front_offset;
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}
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@@ -3862,21 +3862,21 @@ void VulkanCommandProcessor::UpdateSystemConstantValues(
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}
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dirty |= system_constants_.edram_blend_constant[0] !=
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regs[XE_GPU_REG_RB_BLEND_RED].f32;
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regs.Get<float>(XE_GPU_REG_RB_BLEND_RED);
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system_constants_.edram_blend_constant[0] =
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regs[XE_GPU_REG_RB_BLEND_RED].f32;
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regs.Get<float>(XE_GPU_REG_RB_BLEND_RED);
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dirty |= system_constants_.edram_blend_constant[1] !=
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regs[XE_GPU_REG_RB_BLEND_GREEN].f32;
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regs.Get<float>(XE_GPU_REG_RB_BLEND_GREEN);
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system_constants_.edram_blend_constant[1] =
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regs[XE_GPU_REG_RB_BLEND_GREEN].f32;
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regs.Get<float>(XE_GPU_REG_RB_BLEND_GREEN);
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dirty |= system_constants_.edram_blend_constant[2] !=
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regs[XE_GPU_REG_RB_BLEND_BLUE].f32;
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regs.Get<float>(XE_GPU_REG_RB_BLEND_BLUE);
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system_constants_.edram_blend_constant[2] =
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regs[XE_GPU_REG_RB_BLEND_BLUE].f32;
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regs.Get<float>(XE_GPU_REG_RB_BLEND_BLUE);
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dirty |= system_constants_.edram_blend_constant[3] !=
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regs[XE_GPU_REG_RB_BLEND_ALPHA].f32;
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regs.Get<float>(XE_GPU_REG_RB_BLEND_ALPHA);
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system_constants_.edram_blend_constant[3] =
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regs[XE_GPU_REG_RB_BLEND_ALPHA].f32;
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regs.Get<float>(XE_GPU_REG_RB_BLEND_ALPHA);
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}
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if (dirty) {
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@@ -3903,10 +3903,10 @@ bool VulkanCommandProcessor::UpdateBindings(const VulkanShader* vertex_shader,
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// These are the constant base addresses/ranges for shaders.
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// We have these hardcoded right now cause nothing seems to differ on the Xbox
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// 360 (however, OpenGL ES on Adreno 200 on Android has different ranges).
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assert_true(regs[XE_GPU_REG_SQ_VS_CONST].u32 == 0x000FF000 ||
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regs[XE_GPU_REG_SQ_VS_CONST].u32 == 0x00000000);
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assert_true(regs[XE_GPU_REG_SQ_PS_CONST].u32 == 0x000FF100 ||
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regs[XE_GPU_REG_SQ_PS_CONST].u32 == 0x00000000);
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assert_true(regs[XE_GPU_REG_SQ_VS_CONST] == 0x000FF000 ||
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regs[XE_GPU_REG_SQ_VS_CONST] == 0x00000000);
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assert_true(regs[XE_GPU_REG_SQ_PS_CONST] == 0x000FF100 ||
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regs[XE_GPU_REG_SQ_PS_CONST] == 0x00000000);
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// Check if the float constant layout is still the same and get the counts.
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const Shader::ConstantRegisterMap& float_constant_map_vertex =
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vertex_shader->constant_register_map();
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@@ -4001,8 +4001,7 @@ bool VulkanCommandProcessor::UpdateBindings(const VulkanShader* vertex_shader,
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float_constant_map_entry &= ~(1ull << float_constant_index);
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std::memcpy(mapping,
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®s[XE_GPU_REG_SHADER_CONSTANT_000_X + (i << 8) +
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(float_constant_index << 2)]
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.f32,
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(float_constant_index << 2)],
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sizeof(float) * 4);
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mapping += sizeof(float) * 4;
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}
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@@ -4033,8 +4032,7 @@ bool VulkanCommandProcessor::UpdateBindings(const VulkanShader* vertex_shader,
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float_constant_map_entry &= ~(1ull << float_constant_index);
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std::memcpy(mapping,
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®s[XE_GPU_REG_SHADER_CONSTANT_256_X + (i << 8) +
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(float_constant_index << 2)]
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.f32,
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(float_constant_index << 2)],
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sizeof(float) * 4);
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mapping += sizeof(float) * 4;
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}
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@@ -4055,7 +4053,7 @@ bool VulkanCommandProcessor::UpdateBindings(const VulkanShader* vertex_shader,
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return false;
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}
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buffer_info.range = VkDeviceSize(kBoolLoopConstantsSize);
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std::memcpy(mapping, ®s[XE_GPU_REG_SHADER_CONSTANT_BOOL_000_031].u32,
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std::memcpy(mapping, ®s[XE_GPU_REG_SHADER_CONSTANT_BOOL_000_031],
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kBoolLoopConstantsSize);
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current_constant_buffers_up_to_date_ |=
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UINT32_C(1) << SpirvShaderTranslator::kConstantBufferBoolLoop;
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@@ -4073,7 +4071,7 @@ bool VulkanCommandProcessor::UpdateBindings(const VulkanShader* vertex_shader,
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return false;
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}
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buffer_info.range = VkDeviceSize(kFetchConstantsSize);
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std::memcpy(mapping, ®s[XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0].u32,
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std::memcpy(mapping, ®s[XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0],
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kFetchConstantsSize);
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current_constant_buffers_up_to_date_ |=
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UINT32_C(1) << SpirvShaderTranslator::kConstantBufferFetch;
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