[A64/Vector] Scope VMX FPCR in vector helpers
Save and restore FPCR around each VMX FP operation so vector code doesn't leak FPCR state into scalar paths. Drop the DN bit so NaN propagation fixup can inspect original payloads.
This commit is contained in:
Reality
162
src/xenia/cpu/testing/vector_nan_propagation_test.cc
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162
src/xenia/cpu/testing/vector_nan_propagation_test.cc
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/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2026 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "xenia/cpu/testing/util.h"
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using namespace xe;
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using namespace xe::cpu;
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using namespace xe::cpu::hir;
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using namespace xe::cpu::testing;
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using xe::cpu::ppc::PPCContext;
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// =============================================================================
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// PPC NaN propagation rules for VMX vector float operations:
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//
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// 1. If src1 is NaN, result = src1 with bit 22 set (quieted).
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// 2. Else if src2 is NaN, result = src2 with bit 22 set (quieted).
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// 3. Else if the operation itself produces NaN (e.g., inf - inf),
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// result = PPC default QNaN = 0xFFC00000.
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//
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// These tests verify that behavior for VECTOR_ADD with FLOAT32_TYPE.
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// =============================================================================
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// src1 has QNaN in lane 0, src2 is normal → result lane 0 = src1's NaN quieted.
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TEST_CASE("VECTOR_ADD_F32_NAN_SRC1_PROPAGATES", "[instr]") {
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TestFunction test([](HIRBuilder& b) {
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StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), FLOAT32_TYPE));
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b.Return();
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});
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test.Run(
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[](PPCContext* ctx) {
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// QNaN with payload 0x1234 in lane 0; normal values elsewhere.
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ctx->v[4] = vec128i(0x7FC01234, 0x3F800000, 0x40000000, 0x40400000);
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ctx->v[5] = vec128i(0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000);
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},
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[](PPCContext* ctx) {
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auto result = ctx->v[3];
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// Lane 0: src1 NaN wins, bit 22 set, payload preserved.
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REQUIRE((result.u32[0] & 0xFFC00000) == 0x7FC00000);
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REQUIRE((result.u32[0] & 0x003FFFFF) == 0x1234);
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// Lane 1: 1.0 + 1.0 = 2.0
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REQUIRE(result.u32[1] == 0x40000000);
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});
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}
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// src1 is normal, src2 has QNaN → result = src2's NaN quieted.
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TEST_CASE("VECTOR_ADD_F32_NAN_SRC2_PROPAGATES", "[instr]") {
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TestFunction test([](HIRBuilder& b) {
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StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), FLOAT32_TYPE));
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b.Return();
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});
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test.Run(
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[](PPCContext* ctx) {
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ctx->v[4] = vec128i(0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000);
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// QNaN with payload 0x5678 in lane 0.
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ctx->v[5] = vec128i(0x7FC05678, 0x3F800000, 0x3F800000, 0x3F800000);
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},
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[](PPCContext* ctx) {
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auto result = ctx->v[3];
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// Lane 0: src2 NaN wins (src1 was not NaN), payload preserved.
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REQUIRE((result.u32[0] & 0xFFC00000) == 0x7FC00000);
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REQUIRE((result.u32[0] & 0x003FFFFF) == 0x5678);
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});
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}
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// Both src1 and src2 have NaN in the same lane → src1 wins.
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TEST_CASE("VECTOR_ADD_F32_NAN_BOTH_SRC1_WINS", "[instr]") {
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TestFunction test([](HIRBuilder& b) {
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StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), FLOAT32_TYPE));
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b.Return();
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});
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test.Run(
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[](PPCContext* ctx) {
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// src1: QNaN with payload 0xAAAA
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ctx->v[4] = vec128i(0x7FC0AAAA, 0x3F800000, 0x3F800000, 0x3F800000);
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// src2: QNaN with payload 0xBBBB
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ctx->v[5] = vec128i(0x7FC0BBBB, 0x3F800000, 0x3F800000, 0x3F800000);
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},
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[](PPCContext* ctx) {
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auto result = ctx->v[3];
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// src1's NaN wins when both are NaN.
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REQUIRE((result.u32[0] & 0xFFC00000) == 0x7FC00000);
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REQUIRE((result.u32[0] & 0x003FFFFF) == 0x0AAAA);
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});
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}
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// SNaN in src1 → result is src1 with bit 22 SET (quieted to QNaN).
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TEST_CASE("VECTOR_ADD_F32_SNAN_QUIETED", "[instr]") {
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TestFunction test([](HIRBuilder& b) {
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StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), FLOAT32_TYPE));
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b.Return();
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});
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test.Run(
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[](PPCContext* ctx) {
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// SNaN: exponent all 1s, bit 22 = 0, mantissa != 0.
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// 0x7F812345 = SNaN with payload.
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ctx->v[4] = vec128i(0x7F812345, 0x3F800000, 0x3F800000, 0x3F800000);
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ctx->v[5] = vec128i(0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000);
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},
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[](PPCContext* ctx) {
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auto result = ctx->v[3];
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// SNaN quieted: bit 22 forced on, rest of payload preserved.
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REQUIRE(result.u32[0] == (0x7F812345 | 0x00400000));
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});
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}
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// Neither input is NaN, but operation produces NaN (inf + (-inf)).
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// Result should be PPC default QNaN = 0xFFC00000.
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TEST_CASE("VECTOR_ADD_F32_INF_MINUS_INF_DEFAULT_NAN", "[instr]") {
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TestFunction test([](HIRBuilder& b) {
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StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), FLOAT32_TYPE));
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b.Return();
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});
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test.Run(
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[](PPCContext* ctx) {
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// +inf + (-inf) → NaN
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ctx->v[4] = vec128i(0x7F800000, 0x3F800000, 0x3F800000, 0x3F800000);
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ctx->v[5] = vec128i(0xFF800000, 0x3F800000, 0x3F800000, 0x3F800000);
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},
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[](PPCContext* ctx) {
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auto result = ctx->v[3];
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// PPC default QNaN (negative).
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REQUIRE(result.u32[0] == 0xFFC00000);
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// Other lanes: normal 1.0 + 1.0 = 2.0
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REQUIRE(result.u32[1] == 0x40000000);
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});
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}
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// NaN in different lanes — verify per-lane independence.
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TEST_CASE("VECTOR_ADD_F32_NAN_PER_LANE", "[instr]") {
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TestFunction test([](HIRBuilder& b) {
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StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), FLOAT32_TYPE));
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b.Return();
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});
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test.Run(
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[](PPCContext* ctx) {
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// Lane 0: normal + normal
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// Lane 1: NaN in src1
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// Lane 2: NaN in src2
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// Lane 3: inf + (-inf)
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ctx->v[4] = vec128i(0x3F800000, 0x7FC00001, 0x3F800000, 0x7F800000);
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ctx->v[5] = vec128i(0x3F800000, 0x3F800000, 0x7FC00002, 0xFF800000);
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},
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[](PPCContext* ctx) {
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auto result = ctx->v[3];
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// Lane 0: 1.0 + 1.0 = 2.0
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REQUIRE(result.u32[0] == 0x40000000);
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// Lane 1: src1 NaN propagated, quieted.
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REQUIRE((result.u32[1] & 0xFFC00000) == 0x7FC00000);
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REQUIRE((result.u32[1] & 0x003FFFFF) == 0x00001);
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// Lane 2: src2 NaN propagated, quieted.
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REQUIRE((result.u32[2] & 0xFFC00000) == 0x7FC00000);
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REQUIRE((result.u32[2] & 0x003FFFFF) == 0x00002);
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// Lane 3: generated NaN → PPC default.
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REQUIRE(result.u32[3] == 0xFFC00000);
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});
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}
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103
src/xenia/cpu/testing/vmx_fpcr_isolation_test.cc
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103
src/xenia/cpu/testing/vmx_fpcr_isolation_test.cc
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@@ -0,0 +1,103 @@
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/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2026 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "xenia/cpu/testing/util.h"
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#include <cmath>
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using namespace xe;
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using namespace xe::cpu;
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using namespace xe::cpu::hir;
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using namespace xe::cpu::testing;
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using xe::cpu::ppc::PPCContext;
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// =============================================================================
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// FPCR isolation: VMX vector float ops must not leak their FPCR state into
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// subsequent scalar FP operations.
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//
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// The bug: without scoped FPCR save/restore, a VMX op sets FPCR to
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// round-to-nearest + flush-to-zero, and that state persists into the next
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// scalar FP op — overriding whatever rounding mode the scalar path expects.
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// =============================================================================
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TEST_CASE("VMX_FPCR_DOES_NOT_LEAK_INTO_SCALAR", "[backend]") {
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// Strategy:
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// 1. SET_ROUNDING_MODE to toward-positive-infinity (mode 2)
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// 2. Do a VMX vector float add (internally sets FPCR to RN + FZ)
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// 3. Do a scalar float add of 1.0 + 2^-24
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// 4. If FPCR leaked, the scalar add uses round-to-nearest → result = 1.0
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// If FPCR was properly restored, it uses toward-+inf → result > 1.0
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TestFunction test([](HIRBuilder& b) {
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// Set scalar rounding to toward +infinity.
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b.SetRoundingMode(b.LoadConstantInt32(2));
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// VMX vector float add — this touches FPCR internally.
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StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), FLOAT32_TYPE));
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// Now do a scalar float add. If FPCR leaked, this will round-to-nearest.
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auto a = b.Convert(LoadFPR(b, 6), FLOAT32_TYPE);
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auto c = b.Convert(LoadFPR(b, 7), FLOAT32_TYPE);
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auto sum = b.Add(a, c);
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StoreFPR(b, 3, b.Convert(sum, FLOAT64_TYPE));
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b.Return();
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});
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test.Run(
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[](PPCContext* ctx) {
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// Vector inputs — just normal values, we don't care about the result.
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ctx->v[4] = vec128f(1.0f, 2.0f, 3.0f, 4.0f);
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ctx->v[5] = vec128f(5.0f, 6.0f, 7.0f, 8.0f);
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// Scalar inputs: 1.0 + 2^-24 — rounds differently under different
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// modes.
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ctx->f[6] = 1.0;
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ctx->f[7] = std::ldexp(1.0, -24);
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},
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[&test](PPCContext* ctx) {
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auto result = static_cast<float>(ctx->f[3]);
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// Under toward-+infinity, 1.0f + 2^-24 rounds UP to nextafter(1.0f).
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// Under round-to-nearest, it rounds to 1.0f (ties to even).
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float expected = std::nextafterf(1.0f, 2.0f);
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REQUIRE(result == expected);
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// Reset rounding mode for subsequent tests.
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test.processors[0]->backend()->SetGuestRoundingMode(ctx, 0);
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});
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}
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TEST_CASE("VMX_FPCR_DOES_NOT_LEAK_INTO_SCALAR_MULTIPLE_OPS", "[backend]") {
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// Same idea but with two consecutive VMX vector float adds before the
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// scalar op, to verify FPCR is restored after each one.
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TestFunction test([](HIRBuilder& b) {
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b.SetRoundingMode(b.LoadConstantInt32(2)); // toward +inf
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// Two VMX vector float adds back to back.
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StoreVR(b, 3, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 5), FLOAT32_TYPE));
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StoreVR(b, 6, b.VectorAdd(LoadVR(b, 4), LoadVR(b, 3), FLOAT32_TYPE));
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// Scalar add — must still use toward-+inf.
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auto a = b.Convert(LoadFPR(b, 6), FLOAT32_TYPE);
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auto c = b.Convert(LoadFPR(b, 7), FLOAT32_TYPE);
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auto sum = b.Add(a, c);
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StoreFPR(b, 3, b.Convert(sum, FLOAT64_TYPE));
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b.Return();
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});
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test.Run(
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[](PPCContext* ctx) {
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ctx->v[4] = vec128f(1.0f, 2.0f, 3.0f, 4.0f);
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ctx->v[5] = vec128f(5.0f, 6.0f, 7.0f, 8.0f);
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ctx->f[6] = 1.0;
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ctx->f[7] = std::ldexp(1.0, -24);
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},
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[&test](PPCContext* ctx) {
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auto result = static_cast<float>(ctx->f[3]);
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float expected = std::nextafterf(1.0f, 2.0f);
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REQUIRE(result == expected);
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test.processors[0]->backend()->SetGuestRoundingMode(ctx, 0);
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});
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}
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