[GPU] XeSL texture load shaders + minor XeSL cleanup
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155
src/xenia/gpu/shaders/texture_load.xesli
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155
src/xenia/gpu/shaders/texture_load.xesli
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/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2022 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_GPU_SHADERS_TEXTURE_LOAD_XESLI_
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#define XENIA_GPU_SHADERS_TEXTURE_LOAD_XESLI_
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#include "endian.xesli"
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#include "texture_address.xesli"
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xesl_cbuffer_begin(xe_texture_load_constants, set=2, binding=0, b0, space0)
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uint xe_texture_load_is_tiled_3d_endian_scale;
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// Base offset in bytes, resolution-scaled.
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uint xe_texture_load_guest_offset;
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// For tiled textures - row pitch in guest blocks, aligned to 32, unscaled.
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// For linear textures - row pitch in bytes.
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uint xe_texture_load_guest_pitch_aligned;
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// For 3D textures only (ignored otherwise) - aligned to 32, unscaled.
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uint xe_texture_load_guest_z_stride_block_rows_aligned;
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// - std140 vector boundary -
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// If this is a packed mip tail, this is aligned to tile dimensions.
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// Resolution-scaled.
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xesl_uint3 xe_texture_load_size_blocks;
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// Base offset in bytes.
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uint xe_texture_load_host_offset;
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// - std140 vector boundary -
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uint xe_texture_load_host_pitch;
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uint xe_texture_load_height_texels;
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xesl_cbuffer_end(xe_texture_load_constants)
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bool XeTextureLoadIsTiled() {
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#ifdef XE_TEXTURE_LOAD_RESOLUTION_SCALED
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// Only resolved textures can be resolution-scaled, and resolving is only
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// possible to a tiled destination.
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return true;
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#else
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return (xesl_constant(xe_texture_load_constants,
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xe_texture_load_is_tiled_3d_endian_scale) & 1u) != 0u;
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#endif
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}
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bool XeTextureLoadIs3D() {
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return (xesl_constant(xe_texture_load_constants,
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xe_texture_load_is_tiled_3d_endian_scale) & (1u << 1u))
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!= 0u;
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}
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uint XeTextureLoadEndian32() {
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return (xesl_constant(xe_texture_load_constants,
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xe_texture_load_is_tiled_3d_endian_scale) >> 2u) & 3u;
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}
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xesl_uint2 XeTextureLoadResolutionScale() {
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#ifdef XE_TEXTURE_LOAD_RESOLUTION_SCALED
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return (xesl_constant(xe_texture_load_constants,
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xe_texture_load_is_tiled_3d_endian_scale.xx) >>
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xesl_uint2(4u, 6u)) & 3u;
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#else
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return xesl_uint2(1u, 1u);
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#endif
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}
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xesl_uint3 XeTextureLoadSizeBlocks() {
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return xesl_constant(xe_texture_load_constants, xe_texture_load_size_blocks);
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}
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uint XeTextureLoadHostOffset() {
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return xesl_constant(xe_texture_load_constants, xe_texture_load_host_offset);
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}
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uint XeTextureLoadHostPitch() {
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return xesl_constant(xe_texture_load_constants, xe_texture_load_host_pitch);
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}
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uint XeTextureLoadHeightTexels() {
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return xesl_constant(xe_texture_load_constants,
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xe_texture_load_height_texels);
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}
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// bpb and bpb_log2 are separate because bpb may be not a power of 2 (like 96).
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uint XeTextureLoadGuestBlockOffset(xesl_uint3 block_index, uint bpb,
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uint bpb_log2) {
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#ifdef XE_TEXTURE_LOAD_RESOLUTION_SCALED
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// Only resolved textures can be resolution-scaled, and resolving is only
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// possible to a tiled destination.
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return
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xesl_constant(xe_texture_load_constants, xe_texture_load_guest_offset) +
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XeTextureScaledTiledOffset(
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XeTextureLoadIs3D(), block_index,
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xesl_constant(xe_texture_load_constants,
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xe_texture_load_guest_pitch_aligned),
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xesl_constant(xe_texture_load_constants,
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xe_texture_load_guest_z_stride_block_rows_aligned),
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bpb_log2, XeTextureLoadResolutionScale());
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#else
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int block_offset_guest;
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xesl_dont_flatten if (XeTextureLoadIsTiled()) {
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xesl_dont_flatten if (XeTextureLoadIs3D()) {
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block_offset_guest = XeTextureTiledOffset3D(
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xesl_int3(block_index),
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xesl_constant(xe_texture_load_constants,
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xe_texture_load_guest_pitch_aligned),
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xesl_constant(xe_texture_load_constants,
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xe_texture_load_guest_z_stride_block_rows_aligned),
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bpb_log2);
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} else {
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block_offset_guest = XeTextureTiledOffset2D(
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xesl_int2(block_index.xy),
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xesl_constant(xe_texture_load_constants,
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xe_texture_load_guest_pitch_aligned), bpb_log2);
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}
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} else {
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block_offset_guest = XeTextureGuestLinearOffset(
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xesl_int3(block_index),
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xesl_constant(xe_texture_load_constants,
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xe_texture_load_guest_pitch_aligned),
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xesl_constant(xe_texture_load_constants,
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xe_texture_load_guest_z_stride_block_rows_aligned),
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bpb);
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}
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return uint(int(xesl_constant(xe_texture_load_constants,
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xe_texture_load_guest_offset)) +
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block_offset_guest);
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#endif
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}
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// Offset of the beginning of the odd R32G32/R32G32B32A32 load address from the
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// address of the even load, for power-of-two-sized textures.
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uint XeTextureLoadRightConsecutiveBlocksOffset(uint block_x, uint bpb_log2) {
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#ifdef XE_TEXTURE_LOAD_RESOLUTION_SCALED
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return XeTextureScaledRightSubUnitOffsetInConsecutivePair(
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block_x, bpb_log2, XeTextureLoadResolutionScale());
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#else
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uint offset;
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uint consecutive_blocks_log2 =
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XeTextureTiledConsecutiveBlocksLog2(bpb_log2);
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xesl_dont_flatten if (XeTextureLoadIsTiled()) {
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offset = XeTextureTiledOddConsecutiveBlocksOffset(bpb_log2);
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} else {
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offset = 1u << (consecutive_blocks_log2 + bpb_log2);
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}
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return offset;
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#endif
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}
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#endif // XENIA_GPU_SHADERS_TEXTURE_LOAD_XESLI_
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