Attempting to inline a lot of MMIO operations. Works for GPU stuff mainly.

src/xenia/cpu/hir/hir_builder.cc

@@ -1087,6 +1087,23 @@ void HIRBuilder::StoreContext(size_t offset, Value* value) {
   i->src3.value = NULL;
 }
 
+Value* HIRBuilder::LoadMmio(cpu::MMIORange* mmio_range, uint32_t address,
+                            TypeName type) {
+  Instr* i = AppendInstr(OPCODE_LOAD_MMIO_info, 0, AllocValue(type));
+  i->src1.offset = reinterpret_cast<uint64_t>(mmio_range);
+  i->src2.offset = address;
+  i->src3.value = NULL;
+  return i->dest;
+}
+
+void HIRBuilder::StoreMmio(cpu::MMIORange* mmio_range, uint32_t address,
+                           Value* value) {
+  Instr* i = AppendInstr(OPCODE_STORE_MMIO_info, 0);
+  i->src1.offset = reinterpret_cast<uint64_t>(mmio_range);
+  i->src2.offset = address;
+  i->set_src3(value);
+}
+
 Value* HIRBuilder::Load(Value* address, TypeName type, uint32_t load_flags) {
   ASSERT_ADDRESS_TYPE(address);
   Instr* i = AppendInstr(OPCODE_LOAD_info, load_flags, AllocValue(type));

src/xenia/cpu/hir/hir_builder.h

@@ -19,6 +19,7 @@
 #include "xenia/cpu/hir/label.h"
 #include "xenia/cpu/hir/opcodes.h"
 #include "xenia/cpu/hir/value.h"
+#include "xenia/cpu/mmio_handler.h"
 
 namespace xe {
 namespace cpu {
@@ -130,6 +131,9 @@ class HIRBuilder {
   Value* LoadContext(size_t offset, TypeName type);
   void StoreContext(size_t offset, Value* value);
 
+  Value* LoadMmio(cpu::MMIORange* mmio_range, uint32_t address, TypeName type);
+  void StoreMmio(cpu::MMIORange* mmio_range, uint32_t address, Value* value);
+
   Value* Load(Value* address, TypeName type, uint32_t load_flags = 0);
   void Store(Value* address, Value* value, uint32_t store_flags = 0);
   void Memset(Value* address, Value* value, Value* length);

src/xenia/cpu/hir/opcodes.h

@@ -140,6 +140,8 @@ enum Opcode {
   OPCODE_STORE_LOCAL,
   OPCODE_LOAD_CONTEXT,
   OPCODE_STORE_CONTEXT,
+  OPCODE_LOAD_MMIO,
+  OPCODE_STORE_MMIO,
   OPCODE_LOAD,
   OPCODE_STORE,
   OPCODE_MEMSET,
@@ -243,6 +245,8 @@ enum OpcodeSignature {
       (OPCODE_SIG_TYPE_X) | (OPCODE_SIG_TYPE_O << 3) | (OPCODE_SIG_TYPE_V << 6),
   OPCODE_SIG_X_O_V_V = (OPCODE_SIG_TYPE_X) | (OPCODE_SIG_TYPE_O << 3) |
                        (OPCODE_SIG_TYPE_V << 6) | (OPCODE_SIG_TYPE_V << 9),
+  OPCODE_SIG_X_O_O_V = (OPCODE_SIG_TYPE_X) | (OPCODE_SIG_TYPE_O << 3) |
+                       (OPCODE_SIG_TYPE_O << 6) | (OPCODE_SIG_TYPE_V << 9),
   OPCODE_SIG_X_S = (OPCODE_SIG_TYPE_X) | (OPCODE_SIG_TYPE_S << 3),
   OPCODE_SIG_X_V = (OPCODE_SIG_TYPE_X) | (OPCODE_SIG_TYPE_V << 3),
   OPCODE_SIG_X_V_L =
@@ -260,6 +264,8 @@ enum OpcodeSignature {
   OPCODE_SIG_V = (OPCODE_SIG_TYPE_V),
   OPCODE_SIG_V_O = (OPCODE_SIG_TYPE_V) | (OPCODE_SIG_TYPE_O << 3),
   OPCODE_SIG_V_V = (OPCODE_SIG_TYPE_V) | (OPCODE_SIG_TYPE_V << 3),
+  OPCODE_SIG_V_O_O =
+      (OPCODE_SIG_TYPE_V) | (OPCODE_SIG_TYPE_O << 3) | (OPCODE_SIG_TYPE_O << 6),
   OPCODE_SIG_V_V_O =
       (OPCODE_SIG_TYPE_V) | (OPCODE_SIG_TYPE_V << 3) | (OPCODE_SIG_TYPE_O << 6),
   OPCODE_SIG_V_V_O_V = (OPCODE_SIG_TYPE_V) | (OPCODE_SIG_TYPE_V << 3) |

src/xenia/cpu/hir/opcodes.inl

@@ -212,6 +212,18 @@ DEFINE_OPCODE(
     OPCODE_SIG_X_O_V,
     0)
 
+DEFINE_OPCODE(
+    OPCODE_LOAD_MMIO,
+    "load_mmio",
+    OPCODE_SIG_V_O_O,
+    OPCODE_FLAG_MEMORY)
+
+DEFINE_OPCODE(
+  OPCODE_STORE_MMIO,
+  "store_mmio",
+  OPCODE_SIG_X_O_O_V,
+  OPCODE_FLAG_MEMORY)
+
 DEFINE_OPCODE(
     OPCODE_LOAD,
     "load",