Various fixes.
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@@ -1066,7 +1066,7 @@ int Translate_VECTOR_CONVERT_I2F(TranslationContext& ctx, Instr* i) {
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return DispatchToC(ctx, i, IntCode_VECTOR_CONVERT_I2F);
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}
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static uint8_t __lvsl_table[16][16] = {
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static uint8_t __lvsl_table[17][16] = {
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15},
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{ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16},
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{ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17},
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@@ -1083,8 +1083,9 @@ static uint8_t __lvsl_table[16][16] = {
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{13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28},
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{14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29},
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{15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30},
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{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31},
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};
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static uint8_t __lvsr_table[16][16] = {
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static uint8_t __lvsr_table[17][16] = {
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{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31},
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{15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30},
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{14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29},
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@@ -1101,10 +1102,11 @@ static uint8_t __lvsr_table[16][16] = {
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{ 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18},
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{ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17},
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{ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16},
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15},
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};
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uint32_t IntCode_LOAD_VECTOR_SHL(IntCodeState& ics, const IntCode* i) {
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int8_t sh = ics.rf[i->src1_reg].i8;
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int8_t sh = ics.rf[i->src1_reg].i8 & 0x1F;
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vec128_t& dest = ics.rf[i->dest_reg].v128;
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for (int n = 0; n < 16; n++) {
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dest.b16[n] = __lvsl_table[sh][n];
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@@ -1116,9 +1118,9 @@ int Translate_LOAD_VECTOR_SHL(TranslationContext& ctx, Instr* i) {
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}
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uint32_t IntCode_LOAD_VECTOR_SHR(IntCodeState& ics, const IntCode* i) {
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int8_t sh = ics.rf[i->src1_reg].i8;
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int8_t sh = ics.rf[i->src1_reg].i8 & 0x1F;
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vec128_t& dest = ics.rf[i->dest_reg].v128;
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for (int n = 0; n < 4; n++) {
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for (int n = 0; n < 16; n++) {
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dest.b16[n] = __lvsr_table[sh][n];
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}
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return IA_NEXT;
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