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[Base] Post merge fixes

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This commit is contained in:
Gliniak
2025-08-15 16:27:10 +02:00
parent c4bd676c5e
commit 419c0149c9
6 changed files with 29 additions and 25 deletions
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2
src/xenia/gpu/command_processor.cc
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@@ -397,7 +397,7 @@ void CommandProcessor::EnableReadPointerWriteBack(uint32_t ptr,
XE_NOINLINE XE_COLD void CommandProcessor::LogKickoffInitator(uint32_t value) {
cpu::backend::GuestPseudoStackTrace st;
if (logging::internal::ShouldLog(LogLevel::Debug) &&
if (logging::ShouldLog(LogLevel::Debug) &&
kernel_state_->processor()->backend()->PopulatePseudoStacktrace(&st)) {
logging::LoggerBatch<LogLevel::Debug> log_initiator{};

4
src/xenia/gpu/d3d12/deferred_command_list.cc
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@@ -32,8 +32,8 @@ void DeferredCommandList::Execute(ID3D12GraphicsCommandList* command_list,
#if XE_GPU_FINE_GRAINED_DRAW_SCOPES
SCOPE_profile_cpu_f("gpu");
#endif // XE_GPU_FINE_GRAINED_DRAW_SCOPES
const uintmax_t* stream = command_stream_.data();
size_t stream_remaining = command_stream_.size();
const uintmax_t* stream = (const uintmax_t*)command_stream_.data();
size_t stream_remaining = command_stream_.size() / sizeof(uintmax_t);
ID3D12PipelineState* current_pipeline_state = nullptr;
while (stream_remaining != 0) {
const CommandHeader& header =

30
src/xenia/gpu/registers.h
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@@ -131,14 +131,14 @@ union alignas(uint32_t) SQ_PROGRAM_CNTL {
// Ignore the Freedreno a2xx.xml note about the bit 7 for zero registers,
// the fields are 6-bit, not 8-bit, in yamato_registers.h, and games never
// set the bits 7:6.
uint32_t vs_num_reg : 6; // +0, value minus 1
uint32_t _pad_6 : 2; // +6
uint32_t ps_num_reg : 6; // +8, value minus 1
uint32_t _pad_14 : 2; // +14
uint32_t vs_resource : 1; // +16
uint32_t ps_resource : 1; // +17
uint32_t param_gen : 1; // +18
uint32_t gen_index_pix : 1; // +19
uint32_t vs_num_reg : 6; // +0, value minus 1
uint32_t _pad_6 : 2; // +6
uint32_t ps_num_reg : 6; // +8, value minus 1
uint32_t _pad_14 : 2; // +14
uint32_t vs_resource : 1; // +16
uint32_t ps_resource : 1; // +17
uint32_t param_gen : 1; // +18
uint32_t gen_index_pix : 1; // +19
// Interpolator output count minus 1.
uint32_t vs_export_count : 4; // +20, value minus 1
xenos::VertexShaderExportMode vs_export_mode : 3; // +24
@@ -319,12 +319,12 @@ union alignas(uint32_t) VGT_DRAW_INITIATOR {
// R600, it's set to the explicit mode mainly for tessellated draws in games
// (because VGT_OUTPUT_PATH_CNTL where tessellation is enabled is ignored in
// the implicit major mode).
xenos::MajorMode major_mode : 2; // +8
uint32_t _pad_10 : 1; // +10
xenos::IndexFormat index_size : 1; // +11
uint32_t not_eop : 1; // +12
uint32_t _pad_13 : 3; // +13
uint32_t num_indices : 16; // +16
xenos::MajorMode major_mode : 2; // +8
uint32_t _pad_10 : 1; // +10
xenos::IndexFormat index_size : 1; // +11
uint32_t not_eop : 1; // +12
uint32_t _pad_13 : 3; // +13
uint32_t num_indices : 16; // +16
};
static constexpr Register register_index = XE_GPU_REG_VGT_DRAW_INITIATOR;
};
@@ -496,7 +496,7 @@ union alignas(uint32_t) PA_SU_VTX_CNTL {
xenos::PixelCenter pix_center : 1; // +0
xenos::VertexRounding round_mode : 2; // +1
xenos::VertexQuantization quant_mode : 3; // +3
uint32_t _pad_6 : 26; // +6
uint32_t _pad_6 : 26; // +6
};
static constexpr Register register_index = XE_GPU_REG_PA_SU_VTX_CNTL;
};