Add OPCODE_NEGATED_MUL_ADD/OPCODE_NEGATED_MUL_SUB
Proper handling of nans for VMX max/min on x64 (minps/maxps has special behavior depending on the operand order that vmx does not have for vminfp/vmaxfp) Add extremely unintrusive guest code profiler utilizing KUSER_SHARED systemtime. This profiler is disabled on platforms other than windows, and on windows is disabled by default by a cvar Repurpose GUEST_SCRATCH64 stack offset to instead be for storing guest function profile times, define GUEST_SCRATCH as 0 instead, since thats already meant to be a scratch area Fix xenia silently closing on config errors/other fatal errors by setting has_console_attached_'s default to false Add alternative code path for guest clock that uses kusershared systemtime instead of QueryPerformanceCounter. This is way faster and I have tested it and found it to be working, but i have disabled it because i do not know how well it works on wine or on processors other than mine Significantly reduce log spam by setting XELOGAPU and XELOGGPU to be LogLevel::Debug Changed some LOGI to LOGD in places to reduce log spam Mark VdSwap as kHighFrequency, it was spamming up logs Make logging calls less intrusive for the caller by forcing the test of log level inline and moving the format/AppendLogLine stuff to an outlined cold function Add swcache namespace for software cache operations like prefetches, streaming stores and streaming loads. Add XE_MSVC_REORDER_BARRIER for preventing msvc from propagating a value too close to its store or from its load Add xe_unlikely_mutex for locks we know have very little contention add XE_HOST_CACHE_LINE_SIZE and XE_RESTRICT to platform.h Microoptimization: Changed most uses of size_t to ring_size_t in RingBuffer, this reduces the size of the inlined ringbuffer operations slightly by eliminating rex prefixes, depending on register allocation Add BeginPrefetchedRead to ringbuffer, which prefetches the second range if there is one according to the provided PrefetchTag added inline_loadclock cvar, which will directly use the value of the guest clock from clock.cc in jitted guest code. off by default change uses of GUEST_SCRATCH64 to GUEST_SCRATCH Add fast vectorized xenos_half_to_float/xenos_float_to_half (currently resides in x64_seq_vector, move to gpu code maybe at some point) Add fast x64 codegen for PackFloat16_4/UnpackFloat16_4. Same code can be used for Float16_2 in future commit. This should speed up some games that use these functions heavily Remove cvar for toggling old float16 behavior Add VRSAVE register, support mfspr/mtspr vrsave Add cvar for toggling off codegen for trap instructions and set it to true by default. Add specialized methods to CommandProcessor: WriteRegistersFromMem, WriteRegisterRangeFromRing, and WriteOneRegisterFromRing. These reduce the overall cost of WriteRegister Use a fixed size vmem vector for upload ranges, realloc/memsetting on resize in the inner loop of requestranges was showing up on the profiler (the search in requestranges itself needs work) Rename fixed_vmem_vector to better fit xenia's naming convention Only log unknown register writes in WriteRegister if DEBUG :/. We're stuck on MSVC with c++17 so we have no way of influencing the branch ordering for that function without profile guided optimization Remove binding stride assert in shader_translator.cc, triangle told me its leftover ogl stuff Mark xe::FatalError as noreturn If a controller is not connected, delay by 1.1 seconds before checking if it has been reconnected. Asking Xinput about a controller slot that is unused is extremely slow, and XinputGetState/SetState were taking up an enormous amount of time in profiles. this may have caused a bit of input lag Protect accesses to input_system with a lock Add proper handling for user_index>= 4 in XamInputGetState/SetState, properly return zeroed state in GetState Add missing argument to NtQueryVirtualMemory_entry Fixed RtlCompareMemoryUlong_entry, it actually does not care if the source is misaligned, and for length it aligns down Fixed RtlUpperChar and RtlLowerChar, added a table that has their correct return values precomputed
This commit is contained in:
chss95cs@gmail.com
@@ -466,9 +466,11 @@ constexpr inline fourcc_t make_fourcc(const std::string_view fourcc) {
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}
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return make_fourcc(fourcc[0], fourcc[1], fourcc[2], fourcc[3]);
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}
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//chrispy::todo:use for command stream vector, resize happens a ton and has to call memset
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// chrispy::todo:use for command stream vector, resize happens a ton and has to
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// call memset
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template <size_t sz>
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class fixed_vmem_vector {
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class FixedVMemVector {
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static_assert((sz & 65535) == 0,
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"Always give fixed_vmem_vector a size divisible by 65536 to "
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"avoid wasting memory on windows");
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@@ -477,12 +479,12 @@ class fixed_vmem_vector {
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size_t nbytes_;
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public:
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fixed_vmem_vector()
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FixedVMemVector()
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: data_((uint8_t*)memory::AllocFixed(
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nullptr, sz, memory::AllocationType::kReserveCommit,
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memory::PageAccess::kReadWrite)),
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nbytes_(0) {}
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~fixed_vmem_vector() {
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~FixedVMemVector() {
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if (data_) {
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memory::DeallocFixed(data_, sz, memory::DeallocationType::kRelease);
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data_ = nullptr;
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@@ -503,13 +505,221 @@ class fixed_vmem_vector {
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resize(0); // todo:maybe zero out
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}
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void reserve(size_t size) { xenia_assert(size < sz); }
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};
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// software prefetches/cache operations
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namespace swcache {
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/*
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warning, prefetchw's current behavior is not consistent across msvc and
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clang, for clang it will only compile to prefetchw if the set architecture
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supports it, for msvc however it will unconditionally compile to prefetchw!
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so prefetchw support is still in process
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only use these if you're absolutely certain you know what you're doing;
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you can easily tank performance through misuse CPUS have excellent automatic
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prefetchers that can predict patterns, but in situations where memory
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accesses are super unpredictable and follow no pattern you can make use of
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them
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another scenario where it can be handy is when crossing page boundaries,
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as many automatic prefetchers do not allow their streams to cross pages (no
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idea what this means for huge pages)
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I believe software prefetches do not kick off an automatic prefetcher
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stream, so you can't just prefetch one line of the data you're about to
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access and be fine, you need to go all the way
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prefetchnta is implementation dependent, and that makes its use a bit
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limited. For intel cpus, i believe it only prefetches the line into one way
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of the L3
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for amd cpus, it marks the line as requiring immediate eviction, the
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next time an entry is needed in the set it resides in it will be evicted. ms
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does dumb shit for memcpy, like looping over the contents of the source
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buffer and doing prefetchnta on them, likely evicting some of the data they
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just prefetched by the end of the buffer, and probably messing up data that
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was already in the cache
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another warning for these: this bypasses what i think is called
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"critical word load", the data will always become available starting from the
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very beginning of the line instead of from the piece that is needed
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L1I cache is not prefetchable, however likely all cpus can fulfill
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requests for the L1I from L2, so prefetchL2 on instructions should be fine
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todo: clwb, clflush
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*/
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#if XE_COMPILER_HAS_GNU_EXTENSIONS == 1
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XE_FORCEINLINE
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static void PrefetchW(const void* addr) { __builtin_prefetch(addr, 1, 0); }
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XE_FORCEINLINE
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static void PrefetchNTA(const void* addr) { __builtin_prefetch(addr, 0, 0); }
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XE_FORCEINLINE
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static void PrefetchL3(const void* addr) { __builtin_prefetch(addr, 0, 1); }
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XE_FORCEINLINE
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static void PrefetchL2(const void* addr) { __builtin_prefetch(addr, 0, 2); }
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XE_FORCEINLINE
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static void PrefetchL1(const void* addr) { __builtin_prefetch(addr, 0, 3); }
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#elif XE_ARCH_AMD64 == 1 && XE_COMPILER_MSVC == 1
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XE_FORCEINLINE
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static void PrefetchW(const void* addr) { _m_prefetchw(addr); }
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XE_FORCEINLINE
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static void PrefetchNTA(const void* addr) {
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_mm_prefetch((const char*)addr, _MM_HINT_NTA);
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}
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XE_FORCEINLINE
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static void PrefetchL3(const void* addr) {
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_mm_prefetch((const char*)addr, _MM_HINT_T2);
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}
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XE_FORCEINLINE
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static void PrefetchL2(const void* addr) {
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_mm_prefetch((const char*)addr, _MM_HINT_T1);
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}
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XE_FORCEINLINE
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static void PrefetchL1(const void* addr) {
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_mm_prefetch((const char*)addr, _MM_HINT_T0);
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}
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#else
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XE_FORCEINLINE
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static void PrefetchW(const void* addr) {}
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XE_FORCEINLINE
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static void PrefetchNTA(const void* addr) {}
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XE_FORCEINLINE
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static void PrefetchL3(const void* addr) {}
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XE_FORCEINLINE
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static void PrefetchL2(const void* addr) {}
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XE_FORCEINLINE
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static void PrefetchL1(const void* addr) {}
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#endif
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enum class PrefetchTag { Write, Nontemporal, Level3, Level2, Level1 };
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template <PrefetchTag tag>
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static void Prefetch(const void* addr) {
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static_assert(false, "Unknown tag");
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}
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template <>
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static void Prefetch<PrefetchTag::Write>(const void* addr) {
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PrefetchW(addr);
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}
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template <>
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static void Prefetch<PrefetchTag::Nontemporal>(const void* addr) {
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PrefetchNTA(addr);
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}
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template <>
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static void Prefetch<PrefetchTag::Level3>(const void* addr) {
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PrefetchL3(addr);
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}
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template <>
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static void Prefetch<PrefetchTag::Level2>(const void* addr) {
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PrefetchL2(addr);
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}
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template <>
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static void Prefetch<PrefetchTag::Level1>(const void* addr) {
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PrefetchL1(addr);
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}
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// todo: does aarch64 have streaming stores/loads?
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/*
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non-temporal stores/loads
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the stores allow cacheable memory to behave like write-combining memory.
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on the first nt store to a line, an intermediate buffer will be
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allocated by the cpu for stores that come after. once the entire contents of
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the line have been written the intermediate buffer will be transmitted to
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memory
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the written line will not be cached and if it is in the cache it will be
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invalidated from all levels of the hierarchy
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the cpu in this case does not have to read line from memory when we
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first write to it if it is not anywhere in the cache, so we use half the
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memory bandwidth using these stores
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non-temporal loads are... loads, but they dont use the cache. you need
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to manually insert memory barriers (_ReadWriteBarrier, ReadBarrier, etc, do
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not use any barriers that generate actual code) if on msvc to prevent it from
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moving the load of the data to just before the use of the data (immediately
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requiring the memory to be available = big stall)
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*/
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#if XE_COMPILER_MSVC == 1 && XE_COMPILER_CLANG_CL == 0
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#define XE_MSVC_REORDER_BARRIER _ReadWriteBarrier
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#else
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// if the compiler actually has pipelining for instructions we dont need a
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// barrier
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#define XE_MSVC_REORDER_BARRIER() static_cast<void>(0)
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#endif
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#if XE_ARCH_AMD64 == 1
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XE_FORCEINLINE
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static void WriteLineNT(void* destination, const void* source) {
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assert((reinterpret_cast<uintptr_t>(destination) & 63ULL) == 0);
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__m256i low = _mm256_loadu_si256((const __m256i*)source);
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__m256i high = _mm256_loadu_si256(&((const __m256i*)source)[1]);
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XE_MSVC_REORDER_BARRIER();
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_mm256_stream_si256((__m256i*)destination, low);
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_mm256_stream_si256(&((__m256i*)destination)[1], high);
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}
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XE_FORCEINLINE
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static void ReadLineNT(void* destination, const void* source) {
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assert((reinterpret_cast<uintptr_t>(source) & 63ULL) == 0);
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__m256i low = _mm256_stream_load_si256((const __m256i*)source);
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__m256i high = _mm256_stream_load_si256(&((const __m256i*)source)[1]);
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XE_MSVC_REORDER_BARRIER();
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_mm256_storeu_si256((__m256i*)destination, low);
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_mm256_storeu_si256(&((__m256i*)destination)[1], high);
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}
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XE_FORCEINLINE
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static void WriteFence() { _mm_sfence(); }
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XE_FORCEINLINE
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static void ReadFence() { _mm_lfence(); }
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XE_FORCEINLINE
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static void ReadWriteFence() { _mm_mfence(); }
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#else
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XE_FORCEINLINE
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static void WriteLineNT(void* destination, const void* source) {
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assert((reinterpret_cast<uintptr_t>(destination) & 63ULL) == 0);
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memcpy(destination, source, 64);
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}
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XE_FORCEINLINE
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static void ReadLineNT(void* destination, const void* source) {
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assert((reinterpret_cast<uintptr_t>(source) & 63ULL) == 0);
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memcpy(destination, source, 64);
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}
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XE_FORCEINLINE
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static void WriteFence() {}
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XE_FORCEINLINE
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static void ReadFence() {}
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XE_FORCEINLINE
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static void ReadWriteFence() {}
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#endif
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} // namespace swcache
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} // namespace xe
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#endif // XENIA_BASE_MEMORY_H_
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Reference in New Issue
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