A probably-working register allocator.

src/alloy/backend/ivm/ivm_assembler.cc

@@ -74,15 +74,19 @@ int IVMAssembler::Assemble(
   builder->ResetLabelTags();
 
   // Function prologue.
-  size_t stack_size = 0;
+  size_t stack_offset = 0;
   auto locals = builder->locals();
   for (auto it = locals.begin(); it != locals.end(); ++it) {
     auto slot = *it;
-    size_t stack_offset = stack_size;
+    size_t type_size = GetTypeSize(slot->type);
+    // Align to natural size.
+    stack_offset = XEALIGN(stack_offset, type_size);
     slot->set_constant(stack_offset);
-    stack_size += GetTypeSize(slot->type);
+    stack_offset += type_size;
   }
-  ctx.stack_size = stack_size;
+  // Ensure 16b alignment.
+  stack_offset = XEALIGN(stack_offset, 16);
+  ctx.stack_size = stack_offset;
 
   auto block = builder->first_block();
   while (block) {

src/alloy/backend/ivm/ivm_backend.cc

@@ -38,14 +38,14 @@ int IVMBackend::Initialize() {
     0,
     "gpr",
     MachineInfo::RegisterSet::INT_TYPES,
-    10,
+    6,
   };
   machine_info_.register_sets[1] = {
     1,
     "vec",
     MachineInfo::RegisterSet::FLOAT_TYPES |
     MachineInfo::RegisterSet::VEC_TYPES,
-    10,
+    6,
   };
 
   alloy::tracing::WriteEvent(EventType::Init({

src/alloy/backend/x64/x64_emitter.cc

@@ -54,7 +54,7 @@ int X64Emitter::Initialize() {
 }
 
 int X64Emitter::Emit(
-    HIRBuilder* builder, 
+    HIRBuilder* builder,
     uint32_t debug_info_flags, runtime::DebugInfo* debug_info,
     void*& out_code_address, size_t& out_code_size) {
   // Reset.
@@ -98,8 +98,6 @@ void* X64Emitter::Emplace(size_t stack_size) {
   return new_address;
 }
 
-#define XEALIGN(value, align) ((value + align - 1) & ~(align - 1))
-
 int X64Emitter::Emit(HIRBuilder* builder, size_t& out_stack_size) {
   // These are the registers we will not be using. All others are fare game.
   const uint32_t reserved_regs =
@@ -220,7 +218,7 @@ void X64Emitter::ResetRegisters(uint32_t reserved_regs) {
     if (live_regs & 0x1) {
       auto v = reg_state_.reg_values[n];
       if (v) {
-        v->reg = -1;
+        v->reg.index = -1;
       }
     }
     reg_state_.reg_values[n] = 0;