[D3D12] Resolve shader and draw
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@@ -450,6 +450,17 @@ void TextureCache::WriteSampler(uint32_t fetch_constant,
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device->CreateSampler(&desc, handle);
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}
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DXGI_FORMAT TextureCache::GetResolveDXGIFormat(TextureFormat format) {
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// TODO(Triang3l): Change this to a check whether there is a tiling pipeline.
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switch (format) {
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case TextureFormat::k_8_8_8_8:
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return host_formats_[uint32_t(format)].dxgi_format;
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default:
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break;
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}
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return DXGI_FORMAT_UNKNOWN;
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}
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bool TextureCache::RequestSwapTexture(D3D12_CPU_DESCRIPTOR_HANDLE handle) {
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auto group = reinterpret_cast<const xenos::xe_gpu_fetch_group_t*>(
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®ister_file_->values[XE_GPU_REG_SHADER_CONSTANT_FETCH_00_0]);
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@@ -467,6 +478,7 @@ bool TextureCache::RequestSwapTexture(D3D12_CPU_DESCRIPTOR_HANDLE handle) {
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command_processor_->PushTransitionBarrier(
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texture->resource, texture->state,
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D3D12_RESOURCE_STATE_PIXEL_SHADER_RESOURCE);
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texture->state = D3D12_RESOURCE_STATE_PIXEL_SHADER_RESOURCE;
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D3D12_SHADER_RESOURCE_VIEW_DESC srv_desc;
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srv_desc.Format = host_formats_[uint32_t(key.format)].dxgi_format;
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srv_desc.ViewDimension = D3D12_SRV_DIMENSION_TEXTURE2D;
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@@ -826,7 +838,7 @@ bool TextureCache::LoadTextureData(Texture* texture) {
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descriptor_cpu_start.ptr + provider->GetDescriptorSizeView();
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device->CreateUnorderedAccessView(copy_buffer, nullptr, &uav_desc,
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descriptor_cpu_uav);
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command_processor_->SetPipeline(pipeline);
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command_processor_->SetComputePipeline(pipeline);
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command_list->SetComputeRootSignature(copy_root_signature_);
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command_list->SetComputeRootDescriptorTable(1, descriptor_gpu_start);
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