(WIP) SPIR-V Shader Translator
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@@ -32,7 +32,10 @@ class SpirvShaderTranslator : public ShaderTranslator {
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std::vector<uint8_t> CompleteTranslation() override;
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void PostTranslation(Shader* shader) override;
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void PreProcessControlFlowInstruction(uint32_t cf_index) override;
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void ProcessLabel(uint32_t cf_index) override;
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void ProcessControlFlowInstructionBegin(uint32_t cf_index) override;
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void ProcessControlFlowInstructionEnd(uint32_t cf_index) override;
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void ProcessControlFlowNopInstruction() override;
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void ProcessExecInstructionBegin(const ParsedExecInstruction& instr) override;
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void ProcessExecInstructionEnd(const ParsedExecInstruction& instr) override;
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@@ -75,6 +78,27 @@ class SpirvShaderTranslator : public ShaderTranslator {
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// TODO(benvanik): replace with something better, make reusable, etc.
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std::unique_ptr<spv::Builder> builder_;
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spv::Id glsl_std_450_instruction_set_ = 0;
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// Types
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spv::Id float_type_ = 0, bool_type_ = 0;
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spv::Id vec2_float_type_ = 0, vec3_float_type_ = 0, vec4_float_type_ = 0;
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spv::Id vec4_uint_type_ = 0;
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spv::Id vec4_bool_type_ = 0;
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// Constants
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spv::Id vec4_float_zero_ = 0, vec4_float_one_ = 0;
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// Array of AMD registers
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// These values are all pointers.
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spv::Id registers_ptr_ = 0, registers_type_ = 0;
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spv::Id consts_ = 0, a0_ = 0, aL_ = 0, p0_ = 0;
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spv::Id ps_ = 0, pv_ = 0; // IDs of previous results
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spv::Id pos_ = 0;
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spv::Id interpolators_ = 0;
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// Map of {binding -> {offset -> spv input}}
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std::map<uint32_t, std::map<uint32_t, spv::Id>> vertex_binding_map_;
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std::map<uint32_t, spv::Block*> cf_blocks_;
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};
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} // namespace gpu
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