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[D3D12] 32bpp and 20e4 clearing in resolves

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Triang3l
2018-08-25 17:03:06 +03:00
parent 66510b2e6f
commit 50470d67a8
5 changed files with 265 additions and 4 deletions
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25
src/xenia/gpu/d3d12/shaders/edram_clear_32bpp.cs.hlsl Normal file
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@@ -0,0 +1,25 @@
#define XE_EDRAM_WRITE_ONLY
#include "edram_load_store.hlsli"
// Load4/Store4 aren't needed here, but 80x16 threads is over the limit.
[numthreads(40, 16, 1)]
void main(uint3 xe_group_id : SV_GroupID,
uint3 xe_group_thread_id : SV_GroupThreadID,
uint3 xe_thread_id : SV_DispatchThreadID) {
uint4 clear_rect;
clear_rect.xz = xe_edram_clear_rect & 0xFFFFu;
clear_rect.yw = xe_edram_clear_rect >> 16u;
uint2 sample_index = xe_thread_id.xy;
sample_index.x *= 2u;
[branch] if (any(sample_index < clear_rect.xy) ||
any(sample_index >= clear_rect.zw)) {
return;
}
uint2 tile_dword_index = xe_group_thread_id.xy;
tile_dword_index.x *= 2u;
uint edram_offset = XeEDRAMOffset(xe_group_id.xy, tile_dword_index);
xe_edram_load_store_dest.Store(edram_offset, xe_edram_clear_color32);
if (sample_index.x + 1u < clear_rect.z) {
xe_edram_load_store_dest.Store(edram_offset + 4u, xe_edram_clear_color32);
}
}

34
src/xenia/gpu/d3d12/shaders/edram_clear_depth_float.cs.hlsl Normal file
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@@ -0,0 +1,34 @@
#define XE_EDRAM_WRITE_ONLY
#include "edram_load_store.hlsli"
// Load4/Store4 aren't needed here, but 80x16 threads is over the limit.
[numthreads(40, 16, 1)]
void main(uint3 xe_group_id : SV_GroupID,
uint3 xe_group_thread_id : SV_GroupThreadID,
uint3 xe_thread_id : SV_DispatchThreadID) {
uint4 clear_rect;
clear_rect.xz = xe_edram_clear_rect & 0xFFFFu;
clear_rect.yw = xe_edram_clear_rect >> 16u;
uint2 sample_index = xe_thread_id.xy;
sample_index.x *= 2u;
[branch] if (any(sample_index < clear_rect.xy) ||
any(sample_index >= clear_rect.zw)) {
return;
}
uint2 tile_dword_index = xe_group_thread_id.xy;
tile_dword_index.x *= 2u;
bool second_sample_inside = sample_index.x + 1u < clear_rect.z;
// 24-bit depth.
uint edram_offset = XeEDRAMOffset(xe_group_id.xy, tile_dword_index);
xe_edram_load_store_dest.Store(edram_offset, xe_edram_clear_depth24);
[branch] if (second_sample_inside) {
xe_edram_load_store_dest.Store(edram_offset + 4u, xe_edram_clear_depth24);
}
// 32-bit depth (pre-converted on the CPU).
xe_edram_load_store_dest.Store(edram_offset + 10485760u,
xe_edram_clear_depth32);
[branch] if (second_sample_inside) {
xe_edram_load_store_dest.Store(edram_offset + 10485764u,
xe_edram_clear_depth32);
}
}

11
src/xenia/gpu/d3d12/shaders/edram_load_store.hlsli
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@@ -31,7 +31,18 @@ cbuffer XeEDRAMLoadStoreConstants : register(b0) {
// For 64 bits per pixel, it's 1 if need to swap 0:15 and 32:47.
#define xe_edram_tile_sample_dest_info (xe_edram_load_store_constants.w)
// For clearing.
// Left/top of the cleared region (relative to EDRAM base) in the lower 16 bits,
// right/bottom in the upper, in samples.
#define xe_edram_clear_rect (xe_edram_load_store_constants.xy)
#define xe_edram_clear_color32 (xe_edram_load_store_constants.z)
#define xe_edram_clear_color64 (xe_edram_load_store_constants.zw)
#define xe_edram_clear_depth24 (xe_edram_load_store_constants.z)
#define xe_edram_clear_depth32 (xe_edram_load_store_constants.w)
#ifndef XE_EDRAM_WRITE_ONLY
ByteAddressBuffer xe_edram_load_store_source : register(t0);
#endif
RWByteAddressBuffer xe_edram_load_store_dest : register(u0);
uint XeEDRAMOffset(uint2 tile_index, uint2 tile_dword_index) {