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Fixing divdu by constant -1.

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This commit is contained in:
Ben Vanik
2015-05-12 23:09:32 -07:00
parent e7b03042ba
commit 56bd2eee2e
14 changed files with 383 additions and 141 deletions
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134
src/xenia/cpu/frontend/test/bin/instr_addme.dis
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@@ -5,49 +5,109 @@ Disassembly of section .text:
100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr
000000000010000c <test_addme_2>:
10000c: 7c 63 1a 78 xor r3,r3,r3
100010: 7c 63 18 f8 not r3,r3
100014: 30 63 00 01 addic r3,r3,1
100018: 7c 64 01 d4 addme r3,r4
10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr
000000000010000c <test_addme_1_constant>:
10000c: 38 80 00 01 li r4,1
100010: 7c 64 01 d4 addme r3,r4
100014: 7c c0 01 14 adde r6,r0,r0
100018: 4e 80 00 20 blr
0000000000100024 <test_addme_3>:
100024: 7c 64 01 d4 addme r3,r4
100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr
000000000010001c <test_addme_2>:
10001c: 7c 63 1a 78 xor r3,r3,r3
100020: 7c 63 18 f8 not r3,r3
100024: 30 63 00 01 addic r3,r3,1
100028: 7c 64 01 d4 addme r3,r4
10002c: 7c c0 01 14 adde r6,r0,r0
100030: 4e 80 00 20 blr
0000000000100030 <test_addme_4>:
100030: 7c 63 1a 78 xor r3,r3,r3
100034: 7c 63 18 f8 not r3,r3
100038: 30 63 00 01 addic r3,r3,1
10003c: 7c 64 01 d4 addme r3,r4
100040: 7c c0 01 14 adde r6,r0,r0
100044: 4e 80 00 20 blr
0000000000100034 <test_addme_2_constant>:
100034: 38 80 00 01 li r4,1
100038: 7c 63 1a 78 xor r3,r3,r3
10003c: 7c 63 18 f8 not r3,r3
100040: 30 63 00 01 addic r3,r3,1
100044: 7c 64 01 d4 addme r3,r4
100048: 7c c0 01 14 adde r6,r0,r0
10004c: 4e 80 00 20 blr
0000000000100048 <test_addme_5>:
100048: 7c 64 01 d4 addme r3,r4
10004c: 7c c0 01 14 adde r6,r0,r0
100050: 4e 80 00 20 blr
0000000000100050 <test_addme_3>:
100050: 7c 64 01 d4 addme r3,r4
100054: 7c c0 01 14 adde r6,r0,r0
100058: 4e 80 00 20 blr
0000000000100054 <test_addme_6>:
100054: 7c 63 1a 78 xor r3,r3,r3
100058: 7c 63 18 f8 not r3,r3
10005c: 30 63 00 01 addic r3,r3,1
000000000010005c <test_addme_3_constant>:
10005c: 38 80 00 0c li r4,12
100060: 7c 64 01 d4 addme r3,r4
100064: 7c c0 01 14 adde r6,r0,r0
100068: 4e 80 00 20 blr
000000000010006c <test_addme_7>:
10006c: 7c 64 01 d4 addme r3,r4
100070: 7c c0 01 14 adde r6,r0,r0
100074: 4e 80 00 20 blr
000000000010006c <test_addme_4>:
10006c: 7c 63 1a 78 xor r3,r3,r3
100070: 7c 63 18 f8 not r3,r3
100074: 30 63 00 01 addic r3,r3,1
100078: 7c 64 01 d4 addme r3,r4
10007c: 7c c0 01 14 adde r6,r0,r0
100080: 4e 80 00 20 blr
0000000000100078 <test_addme_8>:
100078: 7c 63 1a 78 xor r3,r3,r3
10007c: 7c 63 18 f8 not r3,r3
100080: 30 63 00 01 addic r3,r3,1
100084: 7c 64 01 d4 addme r3,r4
100088: 7c c0 01 14 adde r6,r0,r0
10008c: 4e 80 00 20 blr
0000000000100084 <test_addme_4_constant>:
100084: 38 80 00 0c li r4,12
100088: 7c 63 1a 78 xor r3,r3,r3
10008c: 7c 63 18 f8 not r3,r3
100090: 30 63 00 01 addic r3,r3,1
100094: 7c 64 01 d4 addme r3,r4
100098: 7c c0 01 14 adde r6,r0,r0
10009c: 4e 80 00 20 blr
00000000001000a0 <test_addme_5>:
1000a0: 7c 64 01 d4 addme r3,r4
1000a4: 7c c0 01 14 adde r6,r0,r0
1000a8: 4e 80 00 20 blr
00000000001000ac <test_addme_5_constant>:
1000ac: 38 80 ff ff li r4,-1
1000b0: 7c 64 01 d4 addme r3,r4
1000b4: 7c c0 01 14 adde r6,r0,r0
1000b8: 4e 80 00 20 blr
00000000001000bc <test_addme_6>:
1000bc: 7c 63 1a 78 xor r3,r3,r3
1000c0: 7c 63 18 f8 not r3,r3
1000c4: 30 63 00 01 addic r3,r3,1
1000c8: 7c 64 01 d4 addme r3,r4
1000cc: 7c c0 01 14 adde r6,r0,r0
1000d0: 4e 80 00 20 blr
00000000001000d4 <test_addme_6_constant>:
1000d4: 38 80 ff ff li r4,-1
1000d8: 7c 63 1a 78 xor r3,r3,r3
1000dc: 7c 63 18 f8 not r3,r3
1000e0: 30 63 00 01 addic r3,r3,1
1000e4: 7c 64 01 d4 addme r3,r4
1000e8: 7c c0 01 14 adde r6,r0,r0
1000ec: 4e 80 00 20 blr
00000000001000f0 <test_addme_7>:
1000f0: 7c 64 01 d4 addme r3,r4
1000f4: 7c c0 01 14 adde r6,r0,r0
1000f8: 4e 80 00 20 blr
00000000001000fc <test_addme_7_constant>:
1000fc: 38 80 00 00 li r4,0
100100: 7c 64 01 d4 addme r3,r4
100104: 7c c0 01 14 adde r6,r0,r0
100108: 4e 80 00 20 blr
000000000010010c <test_addme_8>:
10010c: 7c 63 1a 78 xor r3,r3,r3
100110: 7c 63 18 f8 not r3,r3
100114: 30 63 00 01 addic r3,r3,1
100118: 7c 64 01 d4 addme r3,r4
10011c: 7c c0 01 14 adde r6,r0,r0
100120: 4e 80 00 20 blr
0000000000100124 <test_addme_8_constant>:
100124: 38 80 00 00 li r4,0
100128: 7c 63 1a 78 xor r3,r3,r3
10012c: 7c 63 18 f8 not r3,r3
100130: 30 63 00 01 addic r3,r3,1
100134: 7c 64 01 d4 addme r3,r4
100138: 7c c0 01 14 adde r6,r0,r0
10013c: 4e 80 00 20 blr