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Moving around some math macros.

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This commit is contained in:
Ben Vanik
2014-08-16 17:18:20 -07:00
parent 54ce9db743
commit 5b83cf5fd1
23 changed files with 148 additions and 137 deletions
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4
src/alloy/backend/ivm/ivm_assembler.cc
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@@ -78,12 +78,12 @@ int IVMAssembler::Assemble(FunctionInfo* symbol_info, HIRBuilder* builder,
auto slot = *it;
size_t type_size = GetTypeSize(slot->type);
// Align to natural size.
stack_offset = XEALIGN(stack_offset, type_size);
stack_offset = poly::align(stack_offset, type_size);
slot->set_constant((uint32_t)stack_offset);
stack_offset += type_size;
}
// Ensure 16b alignment.
stack_offset = XEALIGN(stack_offset, 16);
stack_offset = poly::align(stack_offset, 16ull);
ctx.stack_size = stack_offset;
auto block = builder->first_block();

7
src/alloy/backend/x64/x64_code_cache_win.cc
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@@ -63,11 +63,11 @@ void* X64CodeCache::PlaceCode(void* machine_code, size_t code_size,
size_t alloc_size = code_size;
// Add unwind info into the allocation size. Keep things 16b aligned.
alloc_size += XEROUNDUP(X64CodeChunk::UNWIND_INFO_SIZE, 16);
alloc_size += poly::round_up(X64CodeChunk::UNWIND_INFO_SIZE, 16);
// Always move the code to land on 16b alignment. We do this by rounding up
// to 16b so that all offsets are aligned.
alloc_size = XEROUNDUP(alloc_size, 16);
alloc_size = poly::round_up(alloc_size, 16);
lock_.lock();
@@ -106,7 +106,8 @@ X64CodeChunk::X64CodeChunk(size_t chunk_size)
buffer = (uint8_t*)VirtualAlloc(NULL, capacity, MEM_RESERVE | MEM_COMMIT,
PAGE_EXECUTE_READWRITE);
fn_table_capacity = (uint32_t)XEROUNDUP(capacity / ESTIMATED_FN_SIZE, 16);
fn_table_capacity =
static_cast<uint32_t>(poly::round_up(capacity / ESTIMATED_FN_SIZE, 16));
size_t table_size = fn_table_capacity * sizeof(RUNTIME_FUNCTION);
fn_table = (RUNTIME_FUNCTION*)xe_malloc(table_size);
fn_table_count = 0;

4
src/alloy/backend/x64/x64_emitter.cc
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@@ -121,13 +121,13 @@ int X64Emitter::Emit(HIRBuilder* builder, size_t& out_stack_size) {
auto slot = *it;
size_t type_size = GetTypeSize(slot->type);
// Align to natural size.
stack_offset = XEALIGN(stack_offset, type_size);
stack_offset = poly::align(stack_offset, type_size);
slot->set_constant((uint32_t)stack_offset);
stack_offset += type_size;
}
// Ensure 16b alignment.
stack_offset -= StackLayout::GUEST_STACK_SIZE;
stack_offset = XEALIGN(stack_offset, 16);
stack_offset = poly::align(stack_offset, 16ull);
// Function prolog.
// Must be 16b aligned.

10
src/alloy/frontend/ppc/ppc_disasm.cc
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@@ -287,13 +287,13 @@ void Disasm_bx(InstrData& i, StringBuffer* str) {
void Disasm_bcx(InstrData& i, StringBuffer* str) {
const char* s0 = i.B.LK ? "lr, " : "";
const char* s1;
if (!XESELECTBITS(i.B.BO, 2, 2)) {
if (!select_bits(i.B.BO, 2, 2)) {
s1 = "ctr, ";
} else {
s1 = "";
}
char s2[8] = {0};
if (!XESELECTBITS(i.B.BO, 4, 4)) {
if (!select_bits(i.B.BO, 4, 4)) {
xesnprintfa(s2, XECOUNT(s2), "cr%d, ", i.B.BI >> 2);
}
uint32_t nia;
@@ -309,7 +309,7 @@ void Disasm_bcctrx(InstrData& i, StringBuffer* str) {
// TODO(benvanik): mnemonics
const char* s0 = i.XL.LK ? "lr, " : "";
char s2[8] = {0};
if (!XESELECTBITS(i.XL.BO, 4, 4)) {
if (!select_bits(i.XL.BO, 4, 4)) {
xesnprintfa(s2, XECOUNT(s2), "cr%d, ", i.XL.BI >> 2);
}
str->Append("%-8s %s%sctr", i.type->name, s0, s2);
@@ -321,13 +321,13 @@ void Disasm_bclrx(InstrData& i, StringBuffer* str) {
name = "blr";
}
const char* s1;
if (!XESELECTBITS(i.XL.BO, 2, 2)) {
if (!select_bits(i.XL.BO, 2, 2)) {
s1 = "ctr, ";
} else {
s1 = "";
}
char s2[8] = {0};
if (!XESELECTBITS(i.XL.BO, 4, 4)) {
if (!select_bits(i.XL.BO, 4, 4)) {
xesnprintfa(s2, XECOUNT(s2), "cr%d, ", i.XL.BI >> 2);
}
str->Append("%-8s %s%s", name, s1, s2);

20
src/alloy/frontend/ppc/ppc_emit_control.cc
View File

@@ -176,7 +176,7 @@ XEEMITTER(bcx, 0x40000000, B)(PPCHIRBuilder& f, InstrData& i) {
// 43210 (real)
Value* ctr_ok = NULL;
if (XESELECTBITS(i.B.BO, 2, 2)) {
if (select_bits(i.B.BO, 2, 2)) {
// Ignore ctr.
} else {
// Decrement counter.
@@ -187,7 +187,7 @@ XEEMITTER(bcx, 0x40000000, B)(PPCHIRBuilder& f, InstrData& i) {
ctr = f.Truncate(ctr, INT32_TYPE);
// TODO(benvanik): could do something similar to cond and avoid the
// is_true/branch_true pairing.
if (XESELECTBITS(i.B.BO, 1, 1)) {
if (select_bits(i.B.BO, 1, 1)) {
ctr_ok = f.IsFalse(ctr);
} else {
ctr_ok = f.IsTrue(ctr);
@@ -196,12 +196,12 @@ XEEMITTER(bcx, 0x40000000, B)(PPCHIRBuilder& f, InstrData& i) {
Value* cond_ok = NULL;
bool not_cond_ok = false;
if (XESELECTBITS(i.B.BO, 4, 4)) {
if (select_bits(i.B.BO, 4, 4)) {
// Ignore cond.
} else {
Value* cr = f.LoadCRField(i.B.BI >> 2, i.B.BI & 3);
cond_ok = cr;
if (XESELECTBITS(i.B.BO, 3, 3)) {
if (select_bits(i.B.BO, 3, 3)) {
// Expect true.
not_cond_ok = false;
} else {
@@ -248,12 +248,12 @@ XEEMITTER(bcctrx, 0x4C000420, XL)(PPCHIRBuilder& f, InstrData& i) {
Value* cond_ok = NULL;
bool not_cond_ok = false;
if (XESELECTBITS(i.XL.BO, 4, 4)) {
if (select_bits(i.XL.BO, 4, 4)) {
// Ignore cond.
} else {
Value* cr = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
cond_ok = cr;
if (XESELECTBITS(i.XL.BO, 3, 3)) {
if (select_bits(i.XL.BO, 3, 3)) {
// Expect true.
not_cond_ok = false;
} else {
@@ -282,7 +282,7 @@ XEEMITTER(bclrx, 0x4C000020, XL)(PPCHIRBuilder& f, InstrData& i) {
// 43210 (real)
Value* ctr_ok = NULL;
if (XESELECTBITS(i.XL.BO, 2, 2)) {
if (select_bits(i.XL.BO, 2, 2)) {
// Ignore ctr.
} else {
// Decrement counter.
@@ -293,7 +293,7 @@ XEEMITTER(bclrx, 0x4C000020, XL)(PPCHIRBuilder& f, InstrData& i) {
ctr = f.Truncate(ctr, INT32_TYPE);
// TODO(benvanik): could do something similar to cond and avoid the
// is_true/branch_true pairing.
if (XESELECTBITS(i.XL.BO, 1, 1)) {
if (select_bits(i.XL.BO, 1, 1)) {
ctr_ok = f.IsFalse(ctr);
} else {
ctr_ok = f.IsTrue(ctr);
@@ -302,12 +302,12 @@ XEEMITTER(bclrx, 0x4C000020, XL)(PPCHIRBuilder& f, InstrData& i) {
Value* cond_ok = NULL;
bool not_cond_ok = false;
if (XESELECTBITS(i.XL.BO, 4, 4)) {
if (select_bits(i.XL.BO, 4, 4)) {
// Ignore cond.
} else {
Value* cr = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
cond_ok = cr;
if (XESELECTBITS(i.XL.BO, 3, 3)) {
if (select_bits(i.XL.BO, 3, 3)) {
// Expect true.
not_cond_ok = false;
} else {

34
src/alloy/frontend/ppc/ppc_instr.cc
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@@ -322,48 +322,48 @@ InstrType* GetInstrType(uint32_t code) {
switch (code >> 26) {
case 4:
// Opcode = 4, index = bits 10-0 (10)
slot = alloy::frontend::ppc::tables::instr_table_4[XESELECTBITS(code, 0,
10)];
slot =
alloy::frontend::ppc::tables::instr_table_4[select_bits(code, 0, 10)];
break;
case 19:
// Opcode = 19, index = bits 10-1 (10)
slot = alloy::frontend::ppc::tables::instr_table_19[XESELECTBITS(code, 1,
10)];
slot = alloy::frontend::ppc::tables::instr_table_19[select_bits(code, 1,
10)];
break;
case 30:
// Opcode = 30, index = bits 4-1 (4)
// Special cased to an uber instruction.
slot = alloy::frontend::ppc::tables::instr_table_30[XESELECTBITS(code, 0,
0)];
slot =
alloy::frontend::ppc::tables::instr_table_30[select_bits(code, 0, 0)];
break;
case 31:
// Opcode = 31, index = bits 10-1 (10)
slot = alloy::frontend::ppc::tables::instr_table_31[XESELECTBITS(code, 1,
10)];
slot = alloy::frontend::ppc::tables::instr_table_31[select_bits(code, 1,
10)];
break;
case 58:
// Opcode = 58, index = bits 1-0 (2)
slot = alloy::frontend::ppc::tables::instr_table_58[XESELECTBITS(code, 0,
1)];
slot =
alloy::frontend::ppc::tables::instr_table_58[select_bits(code, 0, 1)];
break;
case 59:
// Opcode = 59, index = bits 5-1 (5)
slot = alloy::frontend::ppc::tables::instr_table_59[XESELECTBITS(code, 1,
5)];
slot =
alloy::frontend::ppc::tables::instr_table_59[select_bits(code, 1, 5)];
break;
case 62:
// Opcode = 62, index = bits 1-0 (2)
slot = alloy::frontend::ppc::tables::instr_table_62[XESELECTBITS(code, 0,
1)];
slot =
alloy::frontend::ppc::tables::instr_table_62[select_bits(code, 0, 1)];
break;
case 63:
// Opcode = 63, index = bits 10-1 (10)
slot = alloy::frontend::ppc::tables::instr_table_63[XESELECTBITS(code, 1,
10)];
slot = alloy::frontend::ppc::tables::instr_table_63[select_bits(code, 1,
10)];
break;
default:
slot =
alloy::frontend::ppc::tables::instr_table[XESELECTBITS(code, 26, 31)];
alloy::frontend::ppc::tables::instr_table[select_bits(code, 26, 31)];
break;
}
if (slot && slot->opcode) {

8
src/alloy/frontend/ppc/ppc_instr.h
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@@ -23,6 +23,14 @@ namespace alloy {
namespace frontend {
namespace ppc {
inline uint32_t make_bitmask(uint32_t a, uint32_t b) {
return (static_cast<uint32_t>(-1) >> (31 - b)) & ~((1u << a) - 1);
}
inline uint32_t select_bits(uint32_t value, uint32_t a, uint32_t b) {
return (value & make_bitmask(a, b)) >> a;
}
// TODO(benvanik): rename these
typedef enum {
kXEPPCInstrFormatI = 0,

4
src/alloy/frontend/ppc/ppc_instr_tables.h
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@@ -96,7 +96,7 @@ static InstrType** instr_table_prep(InstrType* unprep, int unprep_count, int a,
int prep_count = (int)pow(2.0, b - a + 1);
InstrType** prep = (InstrType**)xe_calloc(prep_count * sizeof(void*));
for (int n = 0; n < unprep_count; n++) {
int ordinal = XESELECTBITS(unprep[n].opcode, a, b);
int ordinal = select_bits(unprep[n].opcode, a, b);
prep[ordinal] = &unprep[n];
}
return prep;
@@ -108,7 +108,7 @@ static InstrType** instr_table_prep_63(InstrType* unprep, int unprep_count,
int prep_count = (int)pow(2.0, b - a + 1);
InstrType** prep = (InstrType**)xe_calloc(prep_count * sizeof(void*));
for (int n = 0; n < unprep_count; n++) {
int ordinal = XESELECTBITS(unprep[n].opcode, a, b);
int ordinal = select_bits(unprep[n].opcode, a, b);
if (unprep[n].format == kXEPPCInstrFormatA) {
// Must splat this into all of the slots that it could be in.
for (int m = 0; m < 32; m++) {

4
src/alloy/frontend/ppc/ppc_scanner.cc
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@@ -50,8 +50,8 @@ int PPCScanner::FindExtents(FunctionInfo* symbol_info) {
XELOGSDB("Analyzing function %.8X...", symbol_info->address());
uint32_t start_address = symbol_info->address();
uint32_t end_address = symbol_info->end_address();
uint32_t start_address = static_cast<uint32_t>(symbol_info->address());
uint32_t end_address = static_cast<uint32_t>(symbol_info->end_address());
uint32_t address = start_address;
uint32_t furthest_target = start_address;
size_t blocks_found = 0;