Fixing stvl/stvr.

2014-10-26 02:01:02 -07:00
parent 9649eb0e8d
commit 5bec5bb203
9 changed files with 44 additions and 16 deletions
--- a/src/alloy/frontend/ppc/test/bin/instr_stvl.bin
+++ b/src/alloy/frontend/ppc/test/bin/instr_stvl.bin
--- a/src/alloy/frontend/ppc/test/bin/instr_stvl.dis
+++ b/src/alloy/frontend/ppc/test/bin/instr_stvl.dis
@@ -7,3 +7,7 @@ Disassembly of section .text:
 0000000000100000 <test_stvl_1>:
  100000:	7c 64 05 0e 	stvlx   v3,r4,r0
  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_stvl_2>:
+  100008:	7c 64 05 0e 	stvlx   v3,r4,r0
+  10000c:	4e 80 00 20 	blr
--- a/src/alloy/frontend/ppc/test/bin/instr_stvl.map
+++ b/src/alloy/frontend/ppc/test/bin/instr_stvl.map
@@ -1 +1,2 @@
 0000000000000000 t test_stvl_1
+0000000000000008 t test_stvl_2
--- a/src/alloy/frontend/ppc/test/bin/instr_stvr.bin
+++ b/src/alloy/frontend/ppc/test/bin/instr_stvr.bin
--- a/src/alloy/frontend/ppc/test/bin/instr_stvr.dis
+++ b/src/alloy/frontend/ppc/test/bin/instr_stvr.dis
@@ -7,3 +7,7 @@ Disassembly of section .text:
 0000000000100000 <test_stvr_1>:
  100000:	7c 64 2d 4e 	stvrx   v3,r4,r5
  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_stvr_2>:
+  100008:	7c 64 05 4e 	stvrx   v3,r4,r0
+  10000c:	4e 80 00 20 	blr
--- a/src/alloy/frontend/ppc/test/bin/instr_stvr.map
+++ b/src/alloy/frontend/ppc/test/bin/instr_stvr.map
@@ -1 +1,2 @@
 0000000000000000 t test_stvr_1
+0000000000000008 t test_stvr_2
--- a/src/alloy/frontend/ppc/test/instr_stvl.s
+++ b/src/alloy/frontend/ppc/test/instr_stvl.s
@@ -7,3 +7,13 @@ test_stvl_1:
  #_ REGISTER_OUT r4 0x1040
  #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
  #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F
+
+test_stvl_2:
+  #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F
+  #_ REGISTER_IN r4 0x1044
+  #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  stvlx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1044
+  #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ MEMORY_OUT 00001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB
--- a/src/alloy/frontend/ppc/test/instr_stvr.s
+++ b/src/alloy/frontend/ppc/test/instr_stvr.s
@@ -11,3 +11,13 @@ test_stvr_1:
  #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
  #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F
  #_ MEMORY_OUT 00001050 00000000 00000000 00000000 00000000
+
+test_stvr_2:
+  #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F
+  #_ REGISTER_IN r4 0x1044
+  #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  stvrx v3, r4, r0
+  blr
+  #_ REGISTER_OUT r4 0x1044
+  #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ MEMORY_OUT 00001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F