Now running up to the first required kernel call.
If memory address validation is turned off it runs a lot further.
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@@ -779,12 +779,13 @@ XEEMITTER(rlwinmx, 0x54000000, M )(FunctionGenerator& g, IRBuilder<>& b, I
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// m <- MASK(MB+32, ME+32)
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// RA <- r & m
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// The compiler will generate a bunch of these for the special case of
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// SH=0, MB=ME
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// Which seems to just select a single bit and set cr0 for use with a branch.
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// The compiler will generate a bunch of these for the special case of SH=0.
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// Which seems to just select some bits and set cr0 for use with a branch.
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// We can detect this and do less work.
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if (!i.M.SH && i.M.MB == i.M.ME) {
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Value* v = b.CreateAnd(g.gpr_value(i.M.RS), 1 << i.M.MB);
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if (!i.M.SH) {
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Value* v = b.CreateAnd(b.CreateTrunc(g.gpr_value(i.M.RS), b.getInt32Ty()),
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b.getInt32(XEMASK(i.M.MB + 32, i.M.ME + 32)));
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v = b.CreateZExt(v, b.getInt64Ty());
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g.update_gpr_value(i.M.RA, v);
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if (i.M.Rc) {
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// With cr0 update.
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@@ -793,20 +794,20 @@ XEEMITTER(rlwinmx, 0x54000000, M )(FunctionGenerator& g, IRBuilder<>& b, I
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return 0;
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}
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// // ROTL32(x, y) = rotl(i64.(x||x), y)
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// Value* v = b.CreateZExt(b.CreateTrunc(g.gpr_value(i.M.RS)), b.getInt64Ty());
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// v = b.CreateOr(b.CreateLShr(v, 32), v);
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// // (v << shift) | (v >> (64 - shift));
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// v = b.CreateOr(b.CreateShl(v, i.M.SH), b.CreateLShr(v, 32 - i.M.SH));
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// v = b.CreateAnd(v, XEMASK(i.M.MB + 32, i.M.ME + 32));
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// ROTL32(x, y) = rotl(i64.(x||x), y)
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Value* v = b.CreateAnd(g.gpr_value(i.M.RS), UINT32_MAX);
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v = b.CreateOr(b.CreateShl(v, 32), v);
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// (v << shift) | (v >> (32 - shift));
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v = b.CreateOr(b.CreateShl(v, i.M.SH), b.CreateLShr(v, 32 - i.M.SH));
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v = b.CreateAnd(v, XEMASK(i.M.MB + 32, i.M.ME + 32));
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g.update_gpr_value(i.M.RA, v);
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// if (i.M.Rc) {
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// // With cr0 update.
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// g.update_cr_with_cond(0, v, b.getInt64(0), true);
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// }
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if (i.M.Rc) {
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// With cr0 update.
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g.update_cr_with_cond(0, v, b.getInt64(0), true);
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}
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XEINSTRNOTIMPLEMENTED();
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return 1;
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return 0;
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}
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XEEMITTER(rlwnmx, 0x5C000000, M )(FunctionGenerator& g, IRBuilder<>& b, InstrData& i) {
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