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More style cleanup.

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This commit is contained in:
Ben Vanik
2015-08-06 20:17:01 -07:00
parent e6461f326c
commit 5e08889d93
76 changed files with 418 additions and 420 deletions
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8
src/xenia/cpu/backend/assembler.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_ASSEMBLER_H_
#define XENIA_BACKEND_ASSEMBLER_H_
#ifndef XENIA_CPU_BACKEND_ASSEMBLER_H_
#define XENIA_CPU_BACKEND_ASSEMBLER_H_
#include <memory>
@@ -30,7 +30,7 @@ class Backend;
class Assembler {
public:
Assembler(Backend* backend);
explicit Assembler(Backend* backend);
virtual ~Assembler();
virtual bool Initialize();
@@ -49,4 +49,4 @@ class Assembler {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_ASSEMBLER_H_
#endif // XENIA_CPU_BACKEND_ASSEMBLER_H_

8
src/xenia/cpu/backend/backend.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_BACKEND_H_
#define XENIA_BACKEND_BACKEND_H_
#ifndef XENIA_CPU_BACKEND_BACKEND_H_
#define XENIA_CPU_BACKEND_BACKEND_H_
#include <memory>
@@ -31,7 +31,7 @@ class CodeCache;
class Backend {
public:
Backend(Processor* processor);
explicit Backend(Processor* processor);
virtual ~Backend();
Processor* processor() const { return processor_; }
@@ -61,4 +61,4 @@ class Backend {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_BACKEND_H_
#endif // XENIA_CPU_BACKEND_BACKEND_H_

6
src/xenia/cpu/backend/code_cache.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_CODE_CACHE_H_
#define XENIA_BACKEND_CODE_CACHE_H_
#ifndef XENIA_CPU_BACKEND_CODE_CACHE_H_
#define XENIA_CPU_BACKEND_CODE_CACHE_H_
#include <string>
@@ -39,4 +39,4 @@ class CodeCache {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_CODE_CACHE_H_
#endif // XENIA_CPU_BACKEND_CODE_CACHE_H_

6
src/xenia/cpu/backend/machine_info.h
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@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_MACHINE_INFO_H_
#define XENIA_BACKEND_MACHINE_INFO_H_
#ifndef XENIA_CPU_BACKEND_MACHINE_INFO_H_
#define XENIA_CPU_BACKEND_MACHINE_INFO_H_
#include <cstdint>
@@ -36,4 +36,4 @@ struct MachineInfo {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_MACHINE_INFO_H_
#endif // XENIA_CPU_BACKEND_MACHINE_INFO_H_

5
src/xenia/cpu/backend/x64/x64_assembler.cc
View File

@@ -26,9 +26,6 @@ namespace cpu {
namespace backend {
namespace x64 {
// TODO(benvanik): remove when enums redefined.
using namespace xe::cpu;
using xe::cpu::hir::HIRBuilder;
X64Assembler::X64Assembler(X64Backend* backend)
@@ -78,7 +75,7 @@ bool X64Assembler::Assemble(GuestFunction* function, HIRBuilder* builder,
void* machine_code = nullptr;
size_t code_size = 0;
if (!emitter_->Emit(function, builder, debug_info_flags, debug_info.get(),
machine_code, code_size, function->source_map())) {
&machine_code, &code_size, &function->source_map())) {
return false;
}

8
src/xenia/cpu/backend/x64/x64_assembler.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_X64_X64_ASSEMBLER_H_
#define XENIA_BACKEND_X64_X64_ASSEMBLER_H_
#ifndef XENIA_CPU_BACKEND_X64_X64_ASSEMBLER_H_
#define XENIA_CPU_BACKEND_X64_X64_ASSEMBLER_H_
#include <memory>
#include <vector>
@@ -28,7 +28,7 @@ class XbyakAllocator;
class X64Assembler : public Assembler {
public:
X64Assembler(X64Backend* backend);
explicit X64Assembler(X64Backend* backend);
~X64Assembler() override;
bool Initialize() override;
@@ -58,4 +58,4 @@ class X64Assembler : public Assembler {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_X64_X64_ASSEMBLER_H_
#endif // XENIA_CPU_BACKEND_X64_X64_ASSEMBLER_H_

2
src/xenia/cpu/backend/x64/x64_backend.cc
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@@ -112,8 +112,6 @@ std::unique_ptr<GuestFunction> X64Backend::CreateGuestFunction(
return std::make_unique<X64Function>(module, address);
}
using namespace Xbyak;
X64ThunkEmitter::X64ThunkEmitter(X64Backend* backend, XbyakAllocator* allocator)
: X64Emitter(backend, allocator) {}

10
src/xenia/cpu/backend/x64/x64_backend.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_X64_X64_BACKEND_H_
#define XENIA_BACKEND_X64_X64_BACKEND_H_
#ifndef XENIA_CPU_BACKEND_X64_X64_BACKEND_H_
#define XENIA_CPU_BACKEND_X64_X64_BACKEND_H_
#include <gflags/gflags.h>
@@ -33,9 +33,9 @@ typedef void (*ResolveFunctionThunk)();
class X64Backend : public Backend {
public:
const static uint32_t kForceReturnAddress = 0x9FFF0000u;
static const uint32_t kForceReturnAddress = 0x9FFF0000u;
X64Backend(Processor* processor);
explicit X64Backend(Processor* processor);
~X64Backend() override;
X64CodeCache* code_cache() const { return code_cache_.get(); }
@@ -74,4 +74,4 @@ class X64Backend : public Backend {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_X64_X64_BACKEND_H_
#endif // XENIA_CPU_BACKEND_X64_X64_BACKEND_H_

17
src/xenia/cpu/backend/x64/x64_code_cache.h
View File

@@ -7,13 +7,14 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_X64_X64_CODE_CACHE_H_
#define XENIA_BACKEND_X64_X64_CODE_CACHE_H_
#ifndef XENIA_CPU_BACKEND_X64_X64_CODE_CACHE_H_
#define XENIA_CPU_BACKEND_X64_X64_CODE_CACHE_H_
#include <atomic>
#include <memory>
#include <mutex>
#include <string>
#include <utility>
#include <vector>
#include "xenia/base/memory.h"
@@ -58,18 +59,18 @@ class X64CodeCache : public CodeCache {
protected:
// All executable code falls within 0x80000000 to 0x9FFFFFFF, so we can
// only map enough for lookups within that range.
const static uint64_t kIndirectionTableBase = 0x80000000;
const static uint64_t kIndirectionTableSize = 0x1FFFFFFF;
static const uint64_t kIndirectionTableBase = 0x80000000;
static const uint64_t kIndirectionTableSize = 0x1FFFFFFF;
// The code range is 512MB, but we know the total code games will have is
// pretty small (dozens of mb at most) and our expansion is reasonablish
// so 256MB should be more than enough.
const static uint64_t kGeneratedCodeBase = 0xA0000000;
const static uint64_t kGeneratedCodeSize = 0x0FFFFFFF;
static const uint64_t kGeneratedCodeBase = 0xA0000000;
static const uint64_t kGeneratedCodeSize = 0x0FFFFFFF;
// This is picked to be high enough to cover whatever we can reasonably
// expect. If we hit issues with this it probably means some corner case
// in analysis triggering.
const static size_t kMaximumFunctionCount = 30000;
static const size_t kMaximumFunctionCount = 30000;
struct UnwindReservation {
size_t data_size = 0;
@@ -119,4 +120,4 @@ class X64CodeCache : public CodeCache {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_X64_X64_CODE_CACHE_H_
#endif // XENIA_CPU_BACKEND_X64_X64_CODE_CACHE_H_

2
src/xenia/cpu/backend/x64/x64_code_cache_win.cc
View File

@@ -31,7 +31,7 @@ namespace x64 {
// Size of unwind info per function.
// TODO(benvanik): move this to emitter.
const static uint32_t kUnwindInfoSize = 4 + (2 * 1 + 2 + 2);
static const uint32_t kUnwindInfoSize = 4 + (2 * 1 + 2 + 2);
class Win32X64CodeCache : public X64CodeCache {
public:

49
src/xenia/cpu/backend/x64/x64_emitter.cc
View File

@@ -42,11 +42,6 @@ namespace cpu {
namespace backend {
namespace x64 {
// TODO(benvanik): remove when enums redefined.
using namespace xe::cpu::hir;
using namespace xe::cpu;
using namespace Xbyak;
using xe::cpu::hir::HIRBuilder;
using xe::cpu::hir::Instr;
@@ -56,7 +51,8 @@ static const size_t kStashOffset = 32;
// static const size_t kStashOffsetHigh = 32 + 32;
const uint32_t X64Emitter::gpr_reg_map_[X64Emitter::GPR_COUNT] = {
Operand::RBX, Operand::R12, Operand::R13, Operand::R14, Operand::R15,
Xbyak::Operand::RBX, Xbyak::Operand::R12, Xbyak::Operand::R13,
Xbyak::Operand::R14, Xbyak::Operand::R15,
};
const uint32_t X64Emitter::xmm_reg_map_[X64Emitter::XMM_COUNT] = {
@@ -64,7 +60,7 @@ const uint32_t X64Emitter::xmm_reg_map_[X64Emitter::XMM_COUNT] = {
};
X64Emitter::X64Emitter(X64Backend* backend, XbyakAllocator* allocator)
: CodeGenerator(kMaxCodeSize, AutoGrow, allocator),
: CodeGenerator(kMaxCodeSize, Xbyak::AutoGrow, allocator),
processor_(backend->processor()),
backend_(backend),
code_cache_(backend->code_cache()),
@@ -90,8 +86,8 @@ X64Emitter::~X64Emitter() = default;
bool X64Emitter::Emit(GuestFunction* function, HIRBuilder* builder,
uint32_t debug_info_flags, DebugInfo* debug_info,
void*& out_code_address, size_t& out_code_size,
std::vector<SourceMapEntry>& out_source_map) {
void** out_code_address, size_t* out_code_size,
std::vector<SourceMapEntry>* out_source_map) {
SCOPE_profile_cpu_f("cpu");
// Reset.
@@ -102,16 +98,16 @@ bool X64Emitter::Emit(GuestFunction* function, HIRBuilder* builder,
// Fill the generator with code.
size_t stack_size = 0;
if (!Emit(builder, stack_size)) {
if (!Emit(builder, &stack_size)) {
return false;
}
// Copy the final code to the cache and relocate it.
out_code_size = getSize();
out_code_address = Emplace(stack_size, function);
*out_code_size = getSize();
*out_code_address = Emplace(stack_size, function);
// Stash source map.
source_map_arena_.CloneContents(&out_source_map);
source_map_arena_.CloneContents(out_source_map);
return true;
}
@@ -129,14 +125,14 @@ void* X64Emitter::Emplace(size_t stack_size, GuestFunction* function) {
} else {
new_address = code_cache_->PlaceHostCode(0, top_, size_, stack_size);
}
top_ = (uint8_t*)new_address;
top_ = reinterpret_cast<uint8_t*>(new_address);
ready();
top_ = old_address;
reset();
return new_address;
}
bool X64Emitter::Emit(HIRBuilder* builder, size_t& out_stack_size) {
bool X64Emitter::Emit(HIRBuilder* builder, size_t* out_stack_size) {
Xbyak::Label epilog_label;
epilog_label_ = &epilog_label;
@@ -169,7 +165,7 @@ bool X64Emitter::Emit(HIRBuilder* builder, size_t& out_stack_size) {
// Adding or changing anything here must be matched!
const size_t stack_size = StackLayout::GUEST_STACK_SIZE + stack_offset;
assert_true((stack_size + 8) % 16 == 0);
out_stack_size = stack_size;
*out_stack_size = stack_size;
stack_size_ = stack_size;
sub(rsp, (uint32_t)stack_size);
mov(qword[rsp + StackLayout::GUEST_RCX_HOME], rcx);
@@ -190,10 +186,10 @@ bool X64Emitter::Emit(HIRBuilder* builder, size_t& out_stack_size) {
static_assert(debug::FunctionTraceData::kFunctionCallerHistoryCount == 4,
"bitmask depends on count");
mov(rax, qword[low_address(&trace_header->function_call_count)]);
and_(rax, B00000011);
and_(rax, 0b00000011);
// Record call history value into slot (guest addr in RDX).
mov(dword[RegExp(uint32_t(uint64_t(
mov(dword[Xbyak::RegExp(uint32_t(uint64_t(
low_address(&trace_header->function_caller_history)))) +
rax * 4],
edx);
@@ -221,7 +217,7 @@ bool X64Emitter::Emit(HIRBuilder* builder, size_t& out_stack_size) {
const Instr* instr = block->instr_head;
while (instr) {
const Instr* new_tail = instr;
if (!SelectSequence(*this, instr, &new_tail)) {
if (!SelectSequence(this, instr, &new_tail)) {
// No sequence found!
assert_always();
XELOGE("Unable to process HIR opcode %s", instr->opcode->name);
@@ -368,7 +364,7 @@ void X64Emitter::Call(const hir::Instr* instr, GuestFunction* function) {
}
// Actually jump/call to rax.
if (instr->flags & CALL_TAIL) {
if (instr->flags & hir::CALL_TAIL) {
// Since we skip the prolog we need to mark the return here.
EmitTraceUserCallReturn();
@@ -385,9 +381,10 @@ void X64Emitter::Call(const hir::Instr* instr, GuestFunction* function) {
}
}
void X64Emitter::CallIndirect(const hir::Instr* instr, const Reg64& reg) {
void X64Emitter::CallIndirect(const hir::Instr* instr,
const Xbyak::Reg64& reg) {
// Check if return.
if (instr->flags & CALL_POSSIBLE_RETURN) {
if (instr->flags & hir::CALL_POSSIBLE_RETURN) {
cmp(reg.cvt32(), dword[rsp + StackLayout::GUEST_RET_ADDR]);
je(epilog_label(), CodeGenerator::T_NEAR);
}
@@ -401,7 +398,7 @@ void X64Emitter::CallIndirect(const hir::Instr* instr, const Reg64& reg) {
mov(eax, dword[ebx]);
// Actually jump/call to rax.
if (instr->flags & CALL_TAIL) {
if (instr->flags & hir::CALL_TAIL) {
// Since we skip the prolog we need to mark the return here.
EmitTraceUserCallReturn();
@@ -550,7 +547,7 @@ bool X64Emitter::ConstantFitsIn32Reg(uint64_t v) {
return false;
}
void X64Emitter::MovMem64(const RegExp& addr, uint64_t v) {
void X64Emitter::MovMem64(const Xbyak::RegExp& addr, uint64_t v) {
if ((v & ~0x7FFFFFFF) == 0) {
// Fits under 31 bits, so just load using normal mov.
mov(qword[addr], v);
@@ -651,7 +648,7 @@ uint32_t X64Emitter::PlaceData(Memory* memory) {
return ptr;
}
Address X64Emitter::GetXmmConstPtr(XmmConst id) {
Xbyak::Address X64Emitter::GetXmmConstPtr(XmmConst id) {
// Load through fixed constant table setup by PlaceData.
return ptr[rdx + backend_->emitter_data() + sizeof(vec128_t) * id];
}
@@ -712,7 +709,7 @@ void X64Emitter::LoadConstantXmm(Xbyak::Xmm dest, double v) {
}
}
Address X64Emitter::StashXmm(int index, const Xmm& r) {
Xbyak::Address X64Emitter::StashXmm(int index, const Xbyak::Xmm& r) {
auto addr = ptr[rsp + kStashOffset + (index * 16)];
vmovups(addr, r);
return addr;

12
src/xenia/cpu/backend/x64/x64_emitter.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_X64_X64_EMITTER_H_
#define XENIA_BACKEND_X64_X64_EMITTER_H_
#ifndef XENIA_CPU_BACKEND_X64_X64_EMITTER_H_
#define XENIA_CPU_BACKEND_X64_X64_EMITTER_H_
#include <vector>
@@ -116,8 +116,8 @@ class X64Emitter : public Xbyak::CodeGenerator {
bool Emit(GuestFunction* function, hir::HIRBuilder* builder,
uint32_t debug_info_flags, DebugInfo* debug_info,
void*& out_code_address, size_t& out_code_size,
std::vector<SourceMapEntry>& out_source_map);
void** out_code_address, size_t* out_code_size,
std::vector<SourceMapEntry>* out_source_map);
static uint32_t PlaceData(Memory* memory);
@@ -196,7 +196,7 @@ class X64Emitter : public Xbyak::CodeGenerator {
protected:
void* Emplace(size_t stack_size, GuestFunction* function = nullptr);
bool Emit(hir::HIRBuilder* builder, size_t& out_stack_size);
bool Emit(hir::HIRBuilder* builder, size_t* out_stack_size);
void EmitGetCurrentThreadId();
void EmitTraceUserCallReturn();
@@ -228,4 +228,4 @@ class X64Emitter : public Xbyak::CodeGenerator {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_X64_X64_EMITTER_H_
#endif // XENIA_CPU_BACKEND_X64_X64_EMITTER_H_

6
src/xenia/cpu/backend/x64/x64_function.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_X64_X64_FUNCTION_H_
#define XENIA_BACKEND_X64_X64_FUNCTION_H_
#ifndef XENIA_CPU_BACKEND_X64_X64_FUNCTION_H_
#define XENIA_CPU_BACKEND_X64_X64_FUNCTION_H_
#include "xenia/cpu/function.h"
#include "xenia/cpu/thread_state.h"
@@ -41,4 +41,4 @@ class X64Function : public GuestFunction {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_X64_X64_FUNCTION_H_
#endif // XENIA_CPU_BACKEND_X64_X64_FUNCTION_H_

40
src/xenia/cpu/backend/x64/x64_sequences.cc
View File

@@ -1477,16 +1477,16 @@ struct ROUND_F32 : Sequence<ROUND_F32, I<OPCODE_ROUND, F32Op, F32Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
switch (i.instr->flags) {
case ROUND_TO_ZERO:
e.vroundss(i.dest, i.src1, B00000011);
e.vroundss(i.dest, i.src1, 0b00000011);
break;
case ROUND_TO_NEAREST:
e.vroundss(i.dest, i.src1, B00000000);
e.vroundss(i.dest, i.src1, 0b00000000);
break;
case ROUND_TO_MINUS_INFINITY:
e.vroundss(i.dest, i.src1, B00000001);
e.vroundss(i.dest, i.src1, 0b00000001);
break;
case ROUND_TO_POSITIVE_INFINITY:
e.vroundss(i.dest, i.src1, B00000010);
e.vroundss(i.dest, i.src1, 0b00000010);
break;
}
}
@@ -1495,16 +1495,16 @@ struct ROUND_F64 : Sequence<ROUND_F64, I<OPCODE_ROUND, F64Op, F64Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
switch (i.instr->flags) {
case ROUND_TO_ZERO:
e.vroundsd(i.dest, i.src1, B00000011);
e.vroundsd(i.dest, i.src1, 0b00000011);
break;
case ROUND_TO_NEAREST:
e.vroundsd(i.dest, i.src1, B00000000);
e.vroundsd(i.dest, i.src1, 0b00000000);
break;
case ROUND_TO_MINUS_INFINITY:
e.vroundsd(i.dest, i.src1, B00000001);
e.vroundsd(i.dest, i.src1, 0b00000001);
break;
case ROUND_TO_POSITIVE_INFINITY:
e.vroundsd(i.dest, i.src1, B00000010);
e.vroundsd(i.dest, i.src1, 0b00000010);
break;
}
}
@@ -1513,16 +1513,16 @@ struct ROUND_V128 : Sequence<ROUND_V128, I<OPCODE_ROUND, V128Op, V128Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) {
switch (i.instr->flags) {
case ROUND_TO_ZERO:
e.vroundps(i.dest, i.src1, B00000011);
e.vroundps(i.dest, i.src1, 0b00000011);
break;
case ROUND_TO_NEAREST:
e.vroundps(i.dest, i.src1, B00000000);
e.vroundps(i.dest, i.src1, 0b00000000);
break;
case ROUND_TO_MINUS_INFINITY:
e.vroundps(i.dest, i.src1, B00000001);
e.vroundps(i.dest, i.src1, 0b00000001);
break;
case ROUND_TO_POSITIVE_INFINITY:
e.vroundps(i.dest, i.src1, B00000010);
e.vroundps(i.dest, i.src1, 0b00000010);
break;
}
}
@@ -4791,7 +4791,7 @@ struct DOT_PRODUCT_3_V128
[](X64Emitter& e, Xmm dest, Xmm src1, Xmm src2) {
// TODO(benvanik): apparently this is very slow
// - find alternative?
e.vdpps(dest, src1, src2, B01110001);
e.vdpps(dest, src1, src2, 0b01110001);
});
}
};
@@ -4809,7 +4809,7 @@ struct DOT_PRODUCT_4_V128
[](X64Emitter& e, Xmm dest, Xmm src1, Xmm src2) {
// TODO(benvanik): apparently this is very slow
// - find alternative?
e.vdpps(dest, src1, src2, B11110001);
e.vdpps(dest, src1, src2, 0b11110001);
});
}
};
@@ -6454,7 +6454,7 @@ struct PACK : Sequence<PACK, I<OPCODE_PACK, V128Op, V128Op, V128Op>> {
if (e.IsFeatureEnabled(kX64EmitF16C)) {
// 0|0|0|0|W|Z|Y|X
e.vcvtps2ph(i.dest, i.dest, B00000011);
e.vcvtps2ph(i.dest, i.dest, 0b00000011);
// Shuffle to X|Y|0|0|0|0|0|0
e.vpshufb(i.dest, i.dest, e.GetXmmConstPtr(XMMPackFLOAT16_2));
} else {
@@ -6481,7 +6481,7 @@ struct PACK : Sequence<PACK, I<OPCODE_PACK, V128Op, V128Op, V128Op>> {
if (e.IsFeatureEnabled(kX64EmitF16C)) {
// 0|0|0|0|W|Z|Y|X
e.vcvtps2ph(i.dest, i.src1, B00000011);
e.vcvtps2ph(i.dest, i.src1, 0b00000011);
// Shuffle to X|Y|Z|W|0|0|0|0
e.vpshufb(i.dest, i.dest, e.GetXmmConstPtr(XMMPackFLOAT16_4));
} else {
@@ -6639,8 +6639,8 @@ struct PACK : Sequence<PACK, I<OPCODE_PACK, V128Op, V128Op, V128Op>> {
src2 = e.xmm0;
}
e.vpackusdw(i.dest, i.src1, src2);
e.vpshuflw(i.dest, i.dest, B10110001);
e.vpshufhw(i.dest, i.dest, B10110001);
e.vpshuflw(i.dest, i.dest, 0b10110001);
e.vpshufhw(i.dest, i.dest, 0b10110001);
} else {
// unsigned -> unsigned
assert_always();
@@ -7125,11 +7125,11 @@ void RegisterSequences() {
Register_OPCODE_ATOMIC_EXCHANGE();
}
bool SelectSequence(X64Emitter& e, const Instr* i, const Instr** new_tail) {
bool SelectSequence(X64Emitter* e, const Instr* i, const Instr** new_tail) {
const InstrKey key(i);
auto it = sequence_table.find(key);
if (it != sequence_table.end()) {
if (it->second(e, i)) {
if (it->second(*e, i)) {
*new_tail = i->next;
return true;
}

16
src/xenia/cpu/backend/x64/x64_sequences.h
View File

@@ -7,16 +7,10 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_X64_X64_SEQUENCES_H_
#define XENIA_BACKEND_X64_X64_SEQUENCES_H_
#ifndef XENIA_CPU_BACKEND_X64_X64_SEQUENCES_H_
#define XENIA_CPU_BACKEND_X64_X64_SEQUENCES_H_
namespace xe {
namespace cpu {
namespace hir {
class Instr;
} // namespace hir
} // namespace cpu
} // namespace xe
#include "xenia/cpu/hir/instr.h"
namespace xe {
namespace cpu {
@@ -26,7 +20,7 @@ namespace x64 {
class X64Emitter;
void RegisterSequences();
bool SelectSequence(X64Emitter& e, const hir::Instr* i,
bool SelectSequence(X64Emitter* e, const hir::Instr* i,
const hir::Instr** new_tail);
} // namespace x64
@@ -34,4 +28,4 @@ bool SelectSequence(X64Emitter& e, const hir::Instr* i,
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_X64_X64_SEQUENCES_H_
#endif // XENIA_CPU_BACKEND_X64_X64_SEQUENCES_H_

16
src/xenia/cpu/backend/x64/x64_stack_layout.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_X64_X64_STACK_LAYOUT_H_
#define XENIA_BACKEND_X64_X64_STACK_LAYOUT_H_
#ifndef XENIA_CPU_BACKEND_X64_X64_STACK_LAYOUT_H_
#define XENIA_CPU_BACKEND_X64_X64_STACK_LAYOUT_H_
#include "xenia/cpu/backend/x64/x64_backend.h"
#include "xenia/cpu/backend/x64/x64_emitter.h"
@@ -115,12 +115,12 @@ namespace x64 {
class StackLayout {
public:
const static size_t THUNK_STACK_SIZE = 120;
static const size_t THUNK_STACK_SIZE = 120;
const static size_t GUEST_STACK_SIZE = 104;
const static size_t GUEST_RCX_HOME = 80;
const static size_t GUEST_RET_ADDR = 88;
const static size_t GUEST_CALL_RET_ADDR = 96;
static const size_t GUEST_STACK_SIZE = 104;
static const size_t GUEST_RCX_HOME = 80;
static const size_t GUEST_RET_ADDR = 88;
static const size_t GUEST_CALL_RET_ADDR = 96;
};
} // namespace x64
@@ -128,4 +128,4 @@ class StackLayout {
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_X64_X64_STACK_LAYOUT_H_
#endif // XENIA_CPU_BACKEND_X64_X64_STACK_LAYOUT_H_

60
src/xenia/cpu/backend/x64/x64_tracers.cc
View File

@@ -58,41 +58,41 @@ uint32_t GetTracingMode() {
}
void TraceString(void* raw_context, const char* str) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
IPRINT("XE[t] :%d: %s\n", thread_state->thread_id(), str);
IFLUSH();
}
void TraceContextLoadI8(void* raw_context, uint64_t offset, uint8_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%d (%X) = ctx i8 +%llu\n", (int8_t)value, value, offset);
}
void TraceContextLoadI16(void* raw_context, uint64_t offset, uint16_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%d (%X) = ctx i16 +%llu\n", (int16_t)value, value, offset);
}
void TraceContextLoadI32(void* raw_context, uint64_t offset, uint32_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%d (%X) = ctx i32 +%llu\n", (int32_t)value, value, offset);
}
void TraceContextLoadI64(void* raw_context, uint64_t offset, uint64_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%lld (%llX) = ctx i64 +%llu\n", (int64_t)value, value, offset);
}
void TraceContextLoadF32(void* raw_context, uint64_t offset, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%e (%X) = ctx f32 +%llu\n", xe::m128_f32<0>(value),
xe::m128_i32<0>(value), offset);
}
void TraceContextLoadF64(void* raw_context, uint64_t offset,
const double* value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
auto v = _mm_loadu_pd(value);
DPRINT("%le (%llX) = ctx f64 +%llu\n", xe::m128_f64<0>(v), xe::m128_i64<0>(v),
offset);
}
void TraceContextLoadV128(void* raw_context, uint64_t offset, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("[%e, %e, %e, %e] [%.8X, %.8X, %.8X, %.8X] = ctx v128 +%llu\n",
xe::m128_f32<0>(value), xe::m128_f32<1>(value), xe::m128_f32<2>(value),
xe::m128_f32<3>(value), xe::m128_i32<0>(value), xe::m128_i32<1>(value),
@@ -100,35 +100,35 @@ void TraceContextLoadV128(void* raw_context, uint64_t offset, __m128 value) {
}
void TraceContextStoreI8(void* raw_context, uint64_t offset, uint8_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("ctx i8 +%llu = %d (%X)\n", offset, (int8_t)value, value);
}
void TraceContextStoreI16(void* raw_context, uint64_t offset, uint16_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("ctx i16 +%llu = %d (%X)\n", offset, (int16_t)value, value);
}
void TraceContextStoreI32(void* raw_context, uint64_t offset, uint32_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("ctx i32 +%llu = %d (%X)\n", offset, (int32_t)value, value);
}
void TraceContextStoreI64(void* raw_context, uint64_t offset, uint64_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("ctx i64 +%llu = %lld (%llX)\n", offset, (int64_t)value, value);
}
void TraceContextStoreF32(void* raw_context, uint64_t offset, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("ctx f32 +%llu = %e (%X)\n", offset, xe::m128_f32<0>(value),
xe::m128_i32<0>(value));
}
void TraceContextStoreF64(void* raw_context, uint64_t offset,
const double* value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
auto v = _mm_loadu_pd(value);
DPRINT("ctx f64 +%llu = %le (%llX)\n", offset, xe::m128_f64<0>(v),
xe::m128_i64<0>(v));
}
void TraceContextStoreV128(void* raw_context, uint64_t offset, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("ctx v128 +%llu = [%e, %e, %e, %e] [%.8X, %.8X, %.8X, %.8X]\n", offset,
xe::m128_f32<0>(value), xe::m128_f32<1>(value), xe::m128_f32<2>(value),
xe::m128_f32<3>(value), xe::m128_i32<0>(value), xe::m128_i32<1>(value),
@@ -136,33 +136,33 @@ void TraceContextStoreV128(void* raw_context, uint64_t offset, __m128 value) {
}
void TraceMemoryLoadI8(void* raw_context, uint32_t address, uint8_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%d (%X) = load.i8 %.8X\n", (int8_t)value, value, address);
}
void TraceMemoryLoadI16(void* raw_context, uint32_t address, uint16_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%d (%X) = load.i16 %.8X\n", (int16_t)value, value, address);
}
void TraceMemoryLoadI32(void* raw_context, uint32_t address, uint32_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%d (%X) = load.i32 %.8X\n", (int32_t)value, value, address);
}
void TraceMemoryLoadI64(void* raw_context, uint32_t address, uint64_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%lld (%llX) = load.i64 %.8X\n", (int64_t)value, value, address);
}
void TraceMemoryLoadF32(void* raw_context, uint32_t address, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%e (%X) = load.f32 %.8X\n", xe::m128_f32<0>(value),
xe::m128_i32<0>(value), address);
}
void TraceMemoryLoadF64(void* raw_context, uint32_t address, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("%le (%llX) = load.f64 %.8X\n", xe::m128_f64<0>(value),
xe::m128_i64<0>(value), address);
}
void TraceMemoryLoadV128(void* raw_context, uint32_t address, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("[%e, %e, %e, %e] [%.8X, %.8X, %.8X, %.8X] = load.v128 %.8X\n",
xe::m128_f32<0>(value), xe::m128_f32<1>(value), xe::m128_f32<2>(value),
xe::m128_f32<3>(value), xe::m128_i32<0>(value), xe::m128_i32<1>(value),
@@ -170,33 +170,33 @@ void TraceMemoryLoadV128(void* raw_context, uint32_t address, __m128 value) {
}
void TraceMemoryStoreI8(void* raw_context, uint32_t address, uint8_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("store.i8 %.8X = %d (%X)\n", address, (int8_t)value, value);
}
void TraceMemoryStoreI16(void* raw_context, uint32_t address, uint16_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("store.i16 %.8X = %d (%X)\n", address, (int16_t)value, value);
}
void TraceMemoryStoreI32(void* raw_context, uint32_t address, uint32_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("store.i32 %.8X = %d (%X)\n", address, (int32_t)value, value);
}
void TraceMemoryStoreI64(void* raw_context, uint32_t address, uint64_t value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("store.i64 %.8X = %lld (%llX)\n", address, (int64_t)value, value);
}
void TraceMemoryStoreF32(void* raw_context, uint32_t address, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("store.f32 %.8X = %e (%X)\n", address, xe::m128_f32<0>(value),
xe::m128_i32<0>(value));
}
void TraceMemoryStoreF64(void* raw_context, uint32_t address, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("store.f64 %.8X = %le (%llX)\n", address, xe::m128_f64<0>(value),
xe::m128_i64<0>(value));
}
void TraceMemoryStoreV128(void* raw_context, uint32_t address, __m128 value) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("store.v128 %.8X = [%e, %e, %e, %e] [%.8X, %.8X, %.8X, %.8X]\n",
address, xe::m128_f32<0>(value), xe::m128_f32<1>(value),
xe::m128_f32<2>(value), xe::m128_f32<3>(value), xe::m128_i32<0>(value),
@@ -206,7 +206,7 @@ void TraceMemoryStoreV128(void* raw_context, uint32_t address, __m128 value) {
void TraceMemset(void* raw_context, uint32_t address, uint8_t value,
uint32_t length) {
auto thread_state = *((ThreadState**)raw_context);
auto thread_state = *reinterpret_cast<ThreadState**>(raw_context);
DPRINT("memset %.8X-%.8X (%d) = %.2X", address, address + length, length,
value);
}

6
src/xenia/cpu/backend/x64/x64_tracers.h
View File

@@ -7,8 +7,8 @@
******************************************************************************
*/
#ifndef XENIA_BACKEND_X64_X64_TRACERS_H_
#define XENIA_BACKEND_X64_X64_TRACERS_H_
#ifndef XENIA_CPU_BACKEND_X64_X64_TRACERS_H_
#define XENIA_CPU_BACKEND_X64_X64_TRACERS_H_
#include <xmmintrin.h>
#include <cstdint>
@@ -72,4 +72,4 @@ void TraceMemset(void* raw_context, uint32_t address, uint8_t value,
} // namespace cpu
} // namespace xe
#endif // XENIA_BACKEND_X64_X64_TRACERS_H_
#endif // XENIA_CPU_BACKEND_X64_X64_TRACERS_H_