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Constant tests for mulhdu, mulhw, mulhwu, mulld, mulli, mullw, neg, nor, ori, rldicl.

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gibbed
2015-05-13 02:38:56 -05:00
parent 6aec2c0d02
commit 5ebd4984ba
10 changed files with 564 additions and 0 deletions
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60
src/xenia/cpu/frontend/test/instr_mulhwu.s
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@@ -7,6 +7,15 @@ test_mulhwu_1:
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhwu_1_constant:
li r4, 1
li r5, 0
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhwu_2:
#_ REGISTER_IN r4 0x00000000FFFFFFFF
#_ REGISTER_IN r5 1
@@ -16,6 +25,16 @@ test_mulhwu_2:
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_2_constant:
li r4, -1
clrldi r4, r4, 32
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_3:
#_ REGISTER_IN r4 0x00000001FFFFFFFF
#_ REGISTER_IN r5 1
@@ -25,6 +44,16 @@ test_mulhwu_3:
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_3_constant:
li r4, -1
clrldi r4, r4, 31
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_4:
#_ REGISTER_IN r4 0x800000007FFFFFFF
#_ REGISTER_IN r5 1
@@ -34,6 +63,19 @@ test_mulhwu_4:
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_4_constant:
li r4, -1
clrldi r4, r4, 33
li r5, 1
sldi r5, r5, 63
or r4, r4, r5
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
@@ -43,6 +85,15 @@ test_mulhwu_5:
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_5_constant:
li r4, -1
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
@@ -51,3 +102,12 @@ test_mulhwu_6:
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhwu_6_constant:
li r4, -1
li r5, -1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF