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Merge branch 'master' into vulkan

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This commit is contained in:
Triang3l
2020-11-21 22:03:50 +03:00
parent cb702b4db2 73dad88429
commit 6288bced48
34 changed files with 1015 additions and 10 deletions
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35
src/xenia/gpu/command_processor.cc
View File

@@ -1179,9 +1179,11 @@ bool CommandProcessor::ExecutePacketType3_DRAW_INDX(RingBuffer* reader,
// initiate fetch of index buffer and draw
// if dword0 != 0, this is a conditional draw based on viz query.
// This ID matches the one issued in PM4_VIZ_QUERY
// ID = dword0 & 0x3F;
// use = dword0 & 0x40;
uint32_t dword0 = reader->ReadAndSwap<uint32_t>(); // viz query info
// uint32_t viz_id = dword0 & 0x3F;
// when true, render conditionally based on query result
// uint32_t viz_use = dword0 & 0x100;
reg::VGT_DRAW_INITIATOR vgt_draw_initiator;
vgt_draw_initiator.value = reader->ReadAndSwap<uint32_t>();
WriteRegister(XE_GPU_REG_VGT_DRAW_INITIATOR, vgt_draw_initiator.value);
@@ -1218,6 +1220,14 @@ bool CommandProcessor::ExecutePacketType3_DRAW_INDX(RingBuffer* reader,
} break;
}
auto viz_query = register_file_->Get<reg::PA_SC_VIZ_QUERY>();
if (viz_query.viz_query_ena && viz_query.kill_pix_post_hi_z) {
// TODO(Triang3l): Don't drop the draw call completely if the vertex shader
// has memexport.
// TODO(Triang3l || JoelLinn): Handle this properly in the render backends.
return true;
}
bool success =
IssueDraw(vgt_draw_initiator.prim_type, vgt_draw_initiator.num_indices,
is_indexed ? &index_buffer_info : nullptr,
@@ -1251,6 +1261,14 @@ bool CommandProcessor::ExecutePacketType3_DRAW_INDX_2(RingBuffer* reader,
// TODO(Triang3l): VGT_IMMED_DATA.
reader->AdvanceRead((count - 1) * sizeof(uint32_t));
auto viz_query = register_file_->Get<reg::PA_SC_VIZ_QUERY>();
if (viz_query.viz_query_ena && viz_query.kill_pix_post_hi_z) {
// TODO(Triang3l): Don't drop the draw call completely if the vertex shader
// has memexport.
// TODO(Triang3l || JoelLinn): Handle this properly in the render backends.
return true;
}
bool success = IssueDraw(
vgt_draw_initiator.prim_type, vgt_draw_initiator.num_indices, nullptr,
xenos::IsMajorModeExplicit(vgt_draw_initiator.major_mode,
@@ -1447,15 +1465,26 @@ bool CommandProcessor::ExecutePacketType3_VIZ_QUERY(RingBuffer* reader,
uint32_t dword0 = reader->ReadAndSwap<uint32_t>();
uint32_t id = dword0 & 0x3F;
uint32_t end = dword0 & 0x80;
uint32_t end = dword0 & 0x100;
if (!end) {
// begin a new viz query @ id
// On hardware this clears the internal state of the scan converter (which
// is different to the register)
WriteRegister(XE_GPU_REG_VGT_EVENT_INITIATOR, VIZQUERY_START);
XELOGGPU("Begin viz query ID {:02X}", id);
} else {
// end the viz query
WriteRegister(XE_GPU_REG_VGT_EVENT_INITIATOR, VIZQUERY_END);
XELOGGPU("End viz query ID {:02X}", id);
// The scan converter writes the internal result back to the register here.
// We just fake it and say it was visible in case it is read back.
if (id < 32) {
register_file_->values[XE_GPU_REG_PA_SC_VIZ_QUERY_STATUS_0].u32 |=
uint32_t(1) << id;
} else {
register_file_->values[XE_GPU_REG_PA_SC_VIZ_QUERY_STATUS_1].u32 |=
uint32_t(1) << (id - 32);
}
}
return true;

213
src/xenia/gpu/register_table.inc
View File

@@ -15,9 +15,25 @@
//#define XE_GPU_REGISTER(index, type, name)
XE_GPU_REGISTER(0x0048, kDword, BIF_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0049, kDword, BIF_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x004A, kDword, BIF_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x01DD, kDword, SCRATCH_ADDR)
XE_GPU_REGISTER(0x01DC, kDword, SCRATCH_UMSK)
XE_GPU_REGISTER(0x01E6, kDword, CP_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x01E7, kDword, CP_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x01E8, kDword, CP_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x01F5, kDword, CP_PERFMON_CNTL)
XE_GPU_REGISTER(0x0395, kDword, RBBM_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0396, kDword, RBBM_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0397, kDword, RBBM_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0398, kDword, RBBM_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0399, kDword, RBBM_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x039A, kDword, RBBM_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x045E, kDword, CALLBACK_ACK)
XE_GPU_REGISTER(0x0578, kDword, SCRATCH_REG0) // interrupt sync
@@ -31,33 +47,226 @@ XE_GPU_REGISTER(0x057F, kDword, SCRATCH_REG7)
XE_GPU_REGISTER(0x05C8, kDword, WAIT_UNTIL)
XE_GPU_REGISTER(0x0815, kDword, MC0_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0816, kDword, MC0_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0817, kDword, MC0_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0855, kDword, MC1_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0856, kDword, MC1_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0857, kDword, MC1_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0A02, kDword, UNKNOWN_0A02)
XE_GPU_REGISTER(0x0A03, kDword, UNKNOWN_0A03)
XE_GPU_REGISTER(0x0A04, kDword, UNKNOWN_0A04)
XE_GPU_REGISTER(0x0A05, kDword, UNKNOWN_0A05)
XE_GPU_REGISTER(0x0A18, kDword, MH_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0A19, kDword, MH_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0A1A, kDword, MH_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0A1B, kDword, MH_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0A1C, kDword, MH_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0A1D, kDword, MH_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0A1E, kDword, MH_PERFCOUNTER2_SELECT)
XE_GPU_REGISTER(0x0A1F, kDword, MH_PERFCOUNTER2_HI)
XE_GPU_REGISTER(0x0A20, kDword, MH_PERFCOUNTER2_LOW)
XE_GPU_REGISTER(0x0A2F, kDword, COHER_SIZE_HOST)
XE_GPU_REGISTER(0x0A30, kDword, COHER_BASE_HOST)
XE_GPU_REGISTER(0x0A31, kDword, COHER_STATUS_HOST)
// Status flags of viz queries, doesn't seem to be read back by d3d
// queries 0x00 to 0x1f (be), bit set when visible
XE_GPU_REGISTER(0x0C44, kDword, PA_SC_VIZ_QUERY_STATUS_0)
// queries 0x20 to 0x3f (be)
XE_GPU_REGISTER(0x0C45, kDword, PA_SC_VIZ_QUERY_STATUS_1)
XE_GPU_REGISTER(0x0C48, kDword, VGT_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0C49, kDword, VGT_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0C4A, kDword, VGT_PERFCOUNTER2_SELECT)
XE_GPU_REGISTER(0x0C4B, kDword, VGT_PERFCOUNTER3_SELECT)
XE_GPU_REGISTER(0x0C4C, kDword, VGT_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0C4D, kDword, VGT_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0C4E, kDword, VGT_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0C4F, kDword, VGT_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0C50, kDword, VGT_PERFCOUNTER2_LOW)
XE_GPU_REGISTER(0x0C51, kDword, VGT_PERFCOUNTER2_HI)
XE_GPU_REGISTER(0x0C52, kDword, VGT_PERFCOUNTER3_LOW)
XE_GPU_REGISTER(0x0C53, kDword, VGT_PERFCOUNTER3_HI)
XE_GPU_REGISTER(0x0C85, kDword, PA_CL_ENHANCE)
XE_GPU_REGISTER(0x0C88, kDword, PA_SU_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0C89, kDword, PA_SU_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0C8A, kDword, PA_SU_PERFCOUNTER2_SELECT)
XE_GPU_REGISTER(0x0C8B, kDword, PA_SU_PERFCOUNTER3_SELECT)
XE_GPU_REGISTER(0x0C8C, kDword, PA_SU_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0C8D, kDword, PA_SU_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0C8E, kDword, PA_SU_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0C8F, kDword, PA_SU_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0C90, kDword, PA_SU_PERFCOUNTER2_LOW)
XE_GPU_REGISTER(0x0C91, kDword, PA_SU_PERFCOUNTER2_HI)
XE_GPU_REGISTER(0x0C92, kDword, PA_SU_PERFCOUNTER3_LOW)
XE_GPU_REGISTER(0x0C93, kDword, PA_SU_PERFCOUNTER3_HI)
XE_GPU_REGISTER(0x0C98, kDword, PA_SC_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0C99, kDword, PA_SC_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0C9A, kDword, PA_SC_PERFCOUNTER2_SELECT)
XE_GPU_REGISTER(0x0C9B, kDword, PA_SC_PERFCOUNTER3_SELECT)
XE_GPU_REGISTER(0x0C9C, kDword, PA_SC_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0C9D, kDword, PA_SC_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0C9E, kDword, PA_SC_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0C9F, kDword, PA_SC_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0CA0, kDword, PA_SC_PERFCOUNTER2_LOW)
XE_GPU_REGISTER(0x0CA1, kDword, PA_SC_PERFCOUNTER2_HI)
XE_GPU_REGISTER(0x0CA2, kDword, PA_SC_PERFCOUNTER3_LOW)
XE_GPU_REGISTER(0x0CA3, kDword, PA_SC_PERFCOUNTER3_HI)
XE_GPU_REGISTER(0x0D00, kDword, SQ_GPR_MANAGEMENT)
XE_GPU_REGISTER(0x0D01, kDword, SQ_FLOW_CONTROL)
XE_GPU_REGISTER(0x0D02, kDword, SQ_INST_STORE_MANAGMENT)
XE_GPU_REGISTER(0x0D04, kDword, SQ_EO_RT)
XE_GPU_REGISTER(0x0C85, kDword, PA_CL_ENHANCE)
XE_GPU_REGISTER(0x0DC8, kDword, SQ_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0DC9, kDword, SQ_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0DCA, kDword, SQ_PERFCOUNTER2_SELECT)
XE_GPU_REGISTER(0x0DCB, kDword, SQ_PERFCOUNTER3_SELECT)
XE_GPU_REGISTER(0x0DCC, kDword, SQ_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0DCD, kDword, SQ_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0DCE, kDword, SQ_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0DCF, kDword, SQ_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0DD0, kDword, SQ_PERFCOUNTER2_LOW)
XE_GPU_REGISTER(0x0DD1, kDword, SQ_PERFCOUNTER2_HI)
XE_GPU_REGISTER(0x0DD2, kDword, SQ_PERFCOUNTER3_LOW)
XE_GPU_REGISTER(0x0DD3, kDword, SQ_PERFCOUNTER3_HI)
XE_GPU_REGISTER(0x0DD4, kDword, SX_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0DD8, kDword, SX_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0DD9, kDword, SX_PERFCOUNTER0_HI)
// Set with WAIT_UNTIL = WAIT_3D_IDLECLEAN
XE_GPU_REGISTER(0x0E00, kDword, UNKNOWN_0E00)
XE_GPU_REGISTER(0x0E05, kDword, TCR_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0E06, kDword, TCR_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0E07, kDword, TCR_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0E08, kDword, TCR_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0E09, kDword, TCR_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0E0A, kDword, TCR_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0E1F, kDword, TP0_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0E20, kDword, TP0_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0E21, kDword, TP0_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0E22, kDword, TP0_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0E23, kDword, TP0_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0E24, kDword, TP0_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0E28, kDword, TP1_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0E29, kDword, TP1_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0E2A, kDword, TP1_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0E2B, kDword, TP1_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0E2C, kDword, TP1_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0E2D, kDword, TP1_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0E31, kDword, TP2_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0E32, kDword, TP2_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0E33, kDword, TP2_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0E34, kDword, TP2_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0E35, kDword, TP2_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0E36, kDword, TP2_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0E3A, kDword, TP3_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0E3B, kDword, TP3_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0E3C, kDword, TP3_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0E3D, kDword, TP3_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0E3E, kDword, TP3_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0E3F, kDword, TP3_PERFCOUNTER1_LOW)
// Set with WAIT_UNTIL = WAIT_3D_IDLECLEAN
XE_GPU_REGISTER(0x0E40, kDword, UNKNOWN_0E40)
// Set during GPU initialization by D3D
XE_GPU_REGISTER(0x0E42, kDword, UNKNOWN_0E42)
XE_GPU_REGISTER(0x0E48, kDword, VC_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0E49, kDword, VC_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0E4A, kDword, VC_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0E4B, kDword, VC_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0E4C, kDword, VC_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0E4D, kDword, VC_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0E4E, kDword, VC_PERFCOUNTER2_SELECT)
XE_GPU_REGISTER(0x0E4F, kDword, VC_PERFCOUNTER2_HI)
XE_GPU_REGISTER(0x0E50, kDword, VC_PERFCOUNTER2_LOW)
XE_GPU_REGISTER(0x0E51, kDword, VC_PERFCOUNTER3_SELECT)
XE_GPU_REGISTER(0x0E52, kDword, VC_PERFCOUNTER3_HI)
XE_GPU_REGISTER(0x0E53, kDword, VC_PERFCOUNTER3_LOW)
XE_GPU_REGISTER(0x0E54, kDword, TCM_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0E55, kDword, TCM_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0E56, kDword, TCM_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0E57, kDword, TCM_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0E58, kDword, TCM_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0E59, kDword, TCM_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0E5A, kDword, TCF_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0E5B, kDword, TCF_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0E5C, kDword, TCF_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0E5D, kDword, TCF_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0E5E, kDword, TCF_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0E5F, kDword, TCF_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0E60, kDword, TCF_PERFCOUNTER2_SELECT)
XE_GPU_REGISTER(0x0E61, kDword, TCF_PERFCOUNTER2_HI)
XE_GPU_REGISTER(0x0E62, kDword, TCF_PERFCOUNTER2_LOW)
XE_GPU_REGISTER(0x0E63, kDword, TCF_PERFCOUNTER3_SELECT)
XE_GPU_REGISTER(0x0E64, kDword, TCF_PERFCOUNTER3_HI)
XE_GPU_REGISTER(0x0E65, kDword, TCF_PERFCOUNTER3_LOW)
XE_GPU_REGISTER(0x0E66, kDword, TCF_PERFCOUNTER4_SELECT)
XE_GPU_REGISTER(0x0E67, kDword, TCF_PERFCOUNTER4_HI)
XE_GPU_REGISTER(0x0E68, kDword, TCF_PERFCOUNTER4_LOW)
XE_GPU_REGISTER(0x0E69, kDword, TCF_PERFCOUNTER5_SELECT)
XE_GPU_REGISTER(0x0E6A, kDword, TCF_PERFCOUNTER5_HI)
XE_GPU_REGISTER(0x0E6B, kDword, TCF_PERFCOUNTER5_LOW)
XE_GPU_REGISTER(0x0E6C, kDword, TCF_PERFCOUNTER6_SELECT)
XE_GPU_REGISTER(0x0E6D, kDword, TCF_PERFCOUNTER6_HI)
XE_GPU_REGISTER(0x0E6E, kDword, TCF_PERFCOUNTER6_LOW)
XE_GPU_REGISTER(0x0E6F, kDword, TCF_PERFCOUNTER7_SELECT)
XE_GPU_REGISTER(0x0E70, kDword, TCF_PERFCOUNTER7_HI)
XE_GPU_REGISTER(0x0E71, kDword, TCF_PERFCOUNTER7_LOW)
XE_GPU_REGISTER(0x0E72, kDword, TCF_PERFCOUNTER8_SELECT)
XE_GPU_REGISTER(0x0E73, kDword, TCF_PERFCOUNTER8_HI)
XE_GPU_REGISTER(0x0E74, kDword, TCF_PERFCOUNTER8_LOW)
XE_GPU_REGISTER(0x0E75, kDword, TCF_PERFCOUNTER9_SELECT)
XE_GPU_REGISTER(0x0E76, kDword, TCF_PERFCOUNTER9_HI)
XE_GPU_REGISTER(0x0E77, kDword, TCF_PERFCOUNTER9_LOW)
XE_GPU_REGISTER(0x0E78, kDword, TCF_PERFCOUNTER10_SELECT)
XE_GPU_REGISTER(0x0E79, kDword, TCF_PERFCOUNTER10_HI)
XE_GPU_REGISTER(0x0E7A, kDword, TCF_PERFCOUNTER10_LOW)
XE_GPU_REGISTER(0x0E7B, kDword, TCF_PERFCOUNTER11_SELECT)
XE_GPU_REGISTER(0x0E7C, kDword, TCF_PERFCOUNTER11_HI)
XE_GPU_REGISTER(0x0E7D, kDword, TCF_PERFCOUNTER11_LOW)
XE_GPU_REGISTER(0x0F01, kDword, RB_BC_CONTROL)
XE_GPU_REGISTER(0x0F02, kDword, RB_EDRAM_INFO)
// D1*, LUT, and AVIVO registers taken from libxenon and https://www.x.org/docs/AMD/old/RRG-216M56-03oOEM.pdf
XE_GPU_REGISTER(0x0F04, kDword, BC_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x0F05, kDword, BC_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x0F06, kDword, BC_PERFCOUNTER2_SELECT)
XE_GPU_REGISTER(0x0F07, kDword, BC_PERFCOUNTER3_SELECT)
XE_GPU_REGISTER(0x0F08, kDword, BC_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x0F09, kDword, BC_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x0F0A, kDword, BC_PERFCOUNTER1_LOW)
XE_GPU_REGISTER(0x0F0B, kDword, BC_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x0F0C, kDword, BC_PERFCOUNTER2_LOW)
XE_GPU_REGISTER(0x0F0D, kDword, BC_PERFCOUNTER2_HI)
XE_GPU_REGISTER(0x0F0E, kDword, BC_PERFCOUNTER3_LOW)
XE_GPU_REGISTER(0x0F0F, kDword, BC_PERFCOUNTER3_HI)
XE_GPU_REGISTER(0x1004, kDword, HZ_PERFCOUNTER0_SELECT)
XE_GPU_REGISTER(0x1005, kDword, HZ_PERFCOUNTER0_HI)
XE_GPU_REGISTER(0x1006, kDword, HZ_PERFCOUNTER0_LOW)
XE_GPU_REGISTER(0x1007, kDword, HZ_PERFCOUNTER1_SELECT)
XE_GPU_REGISTER(0x1008, kDword, HZ_PERFCOUNTER1_HI)
XE_GPU_REGISTER(0x1009, kDword, HZ_PERFCOUNTER1_LOW)
// D1*, LUT, and AVIVO registers taken from libxenon and
// https://www.x.org/docs/AMD/old/RRG-216M56-03oOEM.pdf
XE_GPU_REGISTER(0x1838, kDword, D1MODE_MASTER_UPDATE_LOCK)
XE_GPU_REGISTER(0x1841, kDword, D1GRPH_CONTROL)

12
src/xenia/gpu/registers.h
View File

@@ -289,12 +289,16 @@ union PA_SC_MPASS_PS_CNTL {
static constexpr Register register_index = XE_GPU_REG_PA_SC_MPASS_PS_CNTL;
};
// Scanline converter viz query
// Scanline converter viz query, used by D3D for gpu side conditional rendering
union PA_SC_VIZ_QUERY {
struct {
uint32_t viz_query_ena : 1; // +0
uint32_t viz_query_id : 6; // +1
uint32_t kill_pix_post_early_z : 1; // +7
// the visibility of draws should be evaluated
uint32_t viz_query_ena : 1; // +0
uint32_t viz_query_id : 6; // +1
// discard geometry after test (but use for testing)
uint32_t kill_pix_post_hi_z : 1; // +7
// not used with d3d
uint32_t kill_pix_detail_mask : 1; // +8
};
uint32_t value;
static constexpr Register register_index = XE_GPU_REG_PA_SC_VIZ_QUERY;

5
src/xenia/gpu/xenos.h
View File

@@ -82,7 +82,6 @@ constexpr bool IsPrimitivePolygonal(bool tessellated, PrimitiveType type) {
case PrimitiveType::kTriangleFan:
case PrimitiveType::kTriangleStrip:
case PrimitiveType::kTriangleWithWFlags:
case PrimitiveType::kRectangleList:
case PrimitiveType::kQuadList:
case PrimitiveType::kQuadStrip:
case PrimitiveType::kPolygon:
@@ -90,6 +89,10 @@ constexpr bool IsPrimitivePolygonal(bool tessellated, PrimitiveType type) {
default:
break;
}
// TODO(Triang3l): Investigate how kRectangleList should be treated - possibly
// actually drawn as two polygons on the console, however, the current
// geometry shader doesn't care about the winding order - allowing backface
// culling for rectangles currently breaks Gears of War 2.
return false;
}