Wiring up the LIR flow.

src/alloy/backend/x64/lir/lir_builder.cc

@@ -0,0 +1,32 @@
+/**
+ ******************************************************************************
+ * Xenia : Xbox 360 Emulator Research Project                                 *
+ ******************************************************************************
+ * Copyright 2013 Ben Vanik. All rights reserved.                             *
+ * Released under the BSD license - see LICENSE in the root for more details. *
+ ******************************************************************************
+ */
+
+#include <alloy/backend/x64/lir/lir_builder.h>
+
+using namespace alloy;
+using namespace alloy::backend::x64;
+using namespace alloy::backend::x64::lir;
+
+
+LIRBuilder::LIRBuilder(X64Backend* backend) :
+    backend_(backend) {
+}
+
+LIRBuilder::~LIRBuilder() {
+}
+
+void LIRBuilder::Reset() {
+}
+
+int LIRBuilder::Finalize() {
+  return 0;
+}
+
+void LIRBuilder::Dump(StringBuffer* str) {
+}

src/alloy/backend/x64/lir/lir_builder.h

@@ -17,23 +17,25 @@
 namespace alloy {
 namespace backend {
 namespace x64 {
+class X64Backend;
 namespace lir {
 
 
 class LIRBuilder {
 public:
-  LIRBuilder();
-  virtual ~LIRBuilder();
+  LIRBuilder(X64Backend* backend);
+  ~LIRBuilder();
 
-  virtual void Reset();
-  virtual int Finalize();
+  void Reset();
+  int Finalize();
 
   void Dump(StringBuffer* str);
 
   Arena* arena() const { return arena_; }
 
 protected:
-  Arena*    arena_;
+  X64Backend* backend_;
+  Arena*      arena_;
 };
 
 

src/alloy/backend/x64/lir/lir_opcodes.h

@@ -21,6 +21,12 @@ namespace lir {
 
 enum LIROpcode {
   LIR_OPCODE_MOV_I32,
+  LIR_OPCODE_XOR_I32,
+  LIR_OPCODE_DEC_I32,
+  LIR_OPCODE_SUB_I32,
+  LIR_OPCODE_IMUL_I32,
+  LIR_OPCODE_IMUL_I32_AUX,
+  LIR_OPCODE_DIV_I32,
 
   __LIR_OPCODE_MAX_VALUE, // Keep at end.
 };
@@ -41,6 +47,9 @@ enum LIROpcodeSignatureType {
 
 enum LIROpcodeSignature {
   LIR_OPCODE_SIG_X = (LIR_OPCODE_SIG_TYPE_X),
+  LIR_OPCODE_SIG_R32 = (LIR_OPCODE_SIG_TYPE_X),
+  LIR_OPCODE_SIG_R32_R32 = (LIR_OPCODE_SIG_TYPE_X),
+  LIR_OPCODE_SIG_R32_R32_C32 = (LIR_OPCODE_SIG_TYPE_X),
 };
 
 #define GET_LIR_OPCODE_SIG_TYPE_DEST(sig) (LIROpcodeSignatureType)(sig & 0x7)

src/alloy/backend/x64/lir/lir_opcodes.inl

@@ -7,9 +7,38 @@
  ******************************************************************************
  */
 
-
- DEFINE_OPCODE(
-     LIR_OPCODE_MOV_I32,
-     "mov.i32",
-     LIR_OPCODE_SIG_X,
-     0);
+DEFINE_OPCODE(
+    LIR_OPCODE_MOV_I32,
+    "mov.i32",
+    LIR_OPCODE_SIG_R32_R32,
+    0);
+DEFINE_OPCODE(
+    LIR_OPCODE_XOR_I32,
+    "xor.i32",
+    LIR_OPCODE_SIG_R32_R32,
+    0);
+DEFINE_OPCODE(
+    LIR_OPCODE_DEC_I32,
+    "dec.i32",
+    LIR_OPCODE_SIG_R32,
+    0);
+DEFINE_OPCODE(
+    LIR_OPCODE_SUB_I32,
+    "sub.i32",
+    LIR_OPCODE_SIG_R32_R32,
+    0);
+DEFINE_OPCODE(
+    LIR_OPCODE_IMUL_I32,
+    "imul.i32",
+    LIR_OPCODE_SIG_R32_R32,
+    0);
+DEFINE_OPCODE(
+    LIR_OPCODE_IMUL_I32_AUX,
+    "imul.i32.aux",
+    LIR_OPCODE_SIG_R32_R32_C32,
+    0);
+DEFINE_OPCODE(
+    LIR_OPCODE_DIV_I32,
+    "div.i32",
+    LIR_OPCODE_SIG_R32,
+    0);