Very, very basic branching. Most compares not yet implemented.
This commit is contained in:
Ben Vanik
@@ -24,71 +24,78 @@ namespace cpu {
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namespace x64 {
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// int XeEmitIndirectBranchTo(
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// X64Emitter& e, X86Compiler& c, const char* src, uint32_t cia,
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// bool lk, uint32_t reg) {
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// // TODO(benvanik): run a DFA pass to see if we can detect whether this is
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// // a normal function return that is pulling the LR from the stack that
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// // it set in the prolog. If so, we can omit the dynamic check!
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int XeEmitIndirectBranchTo(
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X64Emitter& e, X86Compiler& c, const char* src, uint32_t cia,
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bool lk, uint32_t reg) {
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// TODO(benvanik): run a DFA pass to see if we can detect whether this is
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// a normal function return that is pulling the LR from the stack that
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// it set in the prolog. If so, we can omit the dynamic check!
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// // NOTE: we avoid spilling registers until we know that the target is not
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// // a basic block within this function.
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// NOTE: we avoid spilling registers until we know that the target is not
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// a basic block within this function.
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// jit_value_t target;
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// switch (reg) {
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// case kXEPPCRegLR:
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// target = e.lr_value();
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// break;
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// case kXEPPCRegCTR:
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// target = e.ctr_value();
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// break;
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// default:
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// XEASSERTALWAYS();
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// return 1;
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// }
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GpVar target;
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switch (reg) {
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case kXEPPCRegLR:
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target = e.lr_value();
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break;
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case kXEPPCRegCTR:
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target = e.ctr_value();
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break;
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default:
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XEASSERTALWAYS();
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return 1;
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}
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// // Dynamic test when branching to LR, which is usually used for the return.
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// // We only do this if LK=0 as returns wouldn't set LR.
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// // Ideally it's a return and we can just do a simple ret and be done.
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// // If it's not, we fall through to the full indirection logic.
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// if (!lk && reg == kXEPPCRegLR) {
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// // The return block will spill registers for us.
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// // TODO(benvanik): 'lr_mismatch' debug info.
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// jit_value_t lr_cmp = jit_insn_eq(f, target, jit_value_get_param(f, 1));
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// e.branch_to_return_if(lr_cmp);
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// }
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// Dynamic test when branching to LR, which is usually used for the return.
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// We only do this if LK=0 as returns wouldn't set LR.
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// Ideally it's a return and we can just do a simple ret and be done.
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// If it's not, we fall through to the full indirection logic.
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if (!lk && reg == kXEPPCRegLR) {
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// The return block will spill registers for us.
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// TODO(benvanik): 'lr_mismatch' debug info.
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c.test(target, c.getGpArg(1));
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// TODO(benvanik): evaluate hint here.
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c.je(e.GetReturnLabel(), kCondHintLikely);
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}
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// // Defer to the generator, which will do fancy things.
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// bool likely_local = !lk && reg == kXEPPCRegCTR;
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// return e.GenerateIndirectionBranch(cia, target, lk, likely_local);
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// }
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// Defer to the generator, which will do fancy things.
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bool likely_local = !lk && reg == kXEPPCRegCTR;
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return e.GenerateIndirectionBranch(cia, target, lk, likely_local);
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}
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int XeEmitBranchTo(
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X64Emitter& e, X86Compiler& c, const char* src, uint32_t cia,
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bool lk, void* condition = NULL) {
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bool lk, GpVar* condition = NULL) {
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FunctionBlock* fn_block = e.fn_block();
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// Fast-path for branches to other blocks.
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// Only valid when not tracing branches.
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if (fn_block->outgoing_type == FunctionBlock::kTargetBlock) {
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if (!FLAGS_trace_branches &&
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fn_block->outgoing_type == FunctionBlock::kTargetBlock) {
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XEASSERT(!lk);
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Label target_label = e.GetBlockLabel(fn_block->outgoing_address);
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if (condition) {
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XEASSERTALWAYS();
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// Fast test -- if condition passed then jump to target.
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// TODO(benvanik): need to spill here? somehow?
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c.test(*condition, *condition);
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c.jnz(target_label);
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} else {
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//e.TraceBranch(cia);
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// TODO(benvanik): need to spill here?
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//e.SpillRegisters();
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//c.jmp(e.GetBlockLabel(fn_block->outgoing_address));
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c.jmp(target_label);
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}
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return 0;
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}
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// Only branch of conditionals when we have one.
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//jit_label_t post_jump_label = jit_label_undefined;
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Label post_jump_label;
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if (condition) {
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// TODO(benvanik): add debug info for this?
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// char name[32];
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// xesnprintfa(name, XECOUNT(name), "loc_%.8X_bcx", i.address);
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//jit_insn_branch_if_not(f, condition, &post_jump_label);
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XEASSERTALWAYS();
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post_jump_label = c.newLabel();
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c.test(*condition, *condition);
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// TODO(benvanik): experiment with various hints?
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c.jz(post_jump_label, kCondHintNone);
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}
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e.TraceBranch(cia);
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@@ -97,9 +104,9 @@ int XeEmitBranchTo(
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int result = 0;
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switch (fn_block->outgoing_type) {
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case FunctionBlock::kTargetBlock:
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// Taken care of above.
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XEASSERTALWAYS();
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result = 1;
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// Often taken care of above, when not tracing branches.
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XEASSERT(!lk);
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c.jmp(e.GetBlockLabel(fn_block->outgoing_address));
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break;
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case FunctionBlock::kTargetFunction:
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{
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@@ -134,18 +141,14 @@ int XeEmitBranchTo(
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{
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// An indirect jump.
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printf("INDIRECT JUMP VIA LR: %.8X\n", cia);
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XEASSERTALWAYS();
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//result = XeEmitIndirectBranchTo(e, c, src, cia, lk, kXEPPCRegLR);
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c.ret();
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result = XeEmitIndirectBranchTo(e, c, src, cia, lk, kXEPPCRegLR);
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break;
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}
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case FunctionBlock::kTargetCTR:
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{
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// An indirect jump.
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printf("INDIRECT JUMP VIA CTR: %.8X\n", cia);
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XEASSERTALWAYS();
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//result = XeEmitIndirectBranchTo(e, c, src, cia, lk, kXEPPCRegCTR);
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c.ret();
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result = XeEmitIndirectBranchTo(e, c, src, cia, lk, kXEPPCRegCTR);
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break;
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}
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default:
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@@ -156,8 +159,7 @@ int XeEmitBranchTo(
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}
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if (condition) {
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XEASSERTALWAYS();
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//jit_insn_label(f, &post_jump_label);
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c.bind(post_jump_label);
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}
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return result;
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@@ -202,61 +204,71 @@ XEEMITTER(bcx, 0x40000000, B )(X64Emitter& e, X86Compiler& c, InstrDat
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// 01234 (docs)
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// 43210 (real)
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// // TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// // The docs say always, though...
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// if (i.B.LK) {
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// e.update_lr_value(e.get_uint64(i.address + 4));
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// }
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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if (i.B.LK) {
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e.update_lr_value(imm(i.address + 4));
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}
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// jit_value_t ctr_ok = NULL;
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// if (XESELECTBITS(i.B.BO, 2, 2)) {
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// // Ignore ctr.
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// } else {
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// // Decrement counter.
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// jit_value_t ctr = e.ctr_value();
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// ctr = jit_insn_sub(f, ctr, e.get_int64(1));
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// e.update_ctr_value(ctr);
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// TODO(benvanik): optimize to just use x64 ops.
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// Need to handle the case where both ctr and cond set.
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// // Ctr check.
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// if (XESELECTBITS(i.B.BO, 1, 1)) {
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// ctr_ok = jit_insn_eq(f, ctr, e.get_int64(0));
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// } else {
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// ctr_ok = jit_insn_ne(f, ctr, e.get_int64(0));
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// }
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// }
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GpVar ctr_ok;
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if (XESELECTBITS(i.B.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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GpVar ctr(c.newGpVar());
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c.mov(ctr, e.ctr_value());
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c.dec(ctr);
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e.update_ctr_value(ctr);
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// jit_value_t cond_ok = NULL;
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// if (XESELECTBITS(i.B.BO, 4, 4)) {
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// // Ignore cond.
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// } else {
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// jit_value_t cr = e.cr_value(i.B.BI >> 2);
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// cr = jit_insn_and(f, cr, e.get_uint32(1 << (i.B.BI & 3)));
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// if (XESELECTBITS(i.B.BO, 3, 3)) {
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// cond_ok = jit_insn_ne(f, cr, e.get_int64(0));
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// } else {
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// cond_ok = jit_insn_eq(f, cr, e.get_int64(0));
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// }
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// }
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// Ctr check.
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c.test(ctr, imm(0));
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ctr_ok = c.newGpVar();
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if (XESELECTBITS(i.B.BO, 1, 1)) {
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c.sete(ctr_ok);
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} else {
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c.setne(ctr_ok);
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}
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}
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// // We do a bit of optimization here to make the llvm assembly easier to read.
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// jit_value_t ok = NULL;
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// if (ctr_ok && cond_ok) {
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// ok = jit_insn_and(f, ctr_ok, cond_ok);
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// } else if (ctr_ok) {
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// ok = ctr_ok;
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// } else if (cond_ok) {
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// ok = cond_ok;
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// }
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GpVar cond_ok;
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if (XESELECTBITS(i.B.BO, 4, 4)) {
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// Ignore cond.
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} else {
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GpVar cr(c.newGpVar());
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c.mov(cr, e.cr_value(i.XL.BI >> 2));
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c.and_(cr, imm(1 << (i.XL.BI & 3)));
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c.test(cr, imm(0));
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cond_ok = c.newGpVar();
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if (XESELECTBITS(i.XL.BO, 3, 3)) {
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c.setne(cond_ok);
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} else {
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c.sete(cond_ok);
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}
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}
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// uint32_t nia;
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// if (i.B.AA) {
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// nia = XEEXTS26(i.B.BD << 2);
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// } else {
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// nia = i.address + XEEXTS26(i.B.BD << 2);
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// }
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// if (XeEmitBranchTo(e, c, "bcx", i.address, i.B.LK, ok)) {
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// return 1;
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// }
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// We do a bit of optimization here to make the llvm assembly easier to read.
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GpVar* ok = NULL;
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if (ctr_ok.getId() != kInvalidValue && cond_ok.getId() != kInvalidValue) {
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c.and_(ctr_ok, cond_ok);
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ok = &ctr_ok;
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} else if (ctr_ok.getId() != kInvalidValue) {
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ok = &ctr_ok;
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} else if (cond_ok.getId() != kInvalidValue) {
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ok = &cond_ok;
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}
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uint32_t nia;
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if (i.B.AA) {
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nia = XEEXTS26(i.B.BD << 2);
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} else {
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nia = i.address + XEEXTS26(i.B.BD << 2);
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}
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if (XeEmitBranchTo(e, c, "bcx", i.address, i.B.LK, ok)) {
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return 1;
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}
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return 0;
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}
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@@ -272,34 +284,37 @@ XEEMITTER(bcctrx, 0x4C000420, XL )(X64Emitter& e, X86Compiler& c, InstrDat
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// 01234 (docs)
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// 43210 (real)
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// // TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// // The docs say always, though...
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// if (i.XL.LK) {
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// e.update_lr_value(e.get_uint64(i.address + 4));
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// }
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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if (i.XL.LK) {
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e.update_lr_value(imm(i.address + 4));
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}
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// jit_value_t cond_ok = NULL;
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// if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// // Ignore cond.
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// } else {
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// jit_value_t cr = e.cr_value(i.XL.BI >> 2);
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// cr = jit_insn_and(f, cr, e.get_uint64(1 << (i.XL.BI & 3)));
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// if (XESELECTBITS(i.XL.BO, 3, 3)) {
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// cond_ok = jit_insn_ne(f, cr, e.get_int64(0));
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// } else {
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// cond_ok = jit_insn_eq(f, cr, e.get_int64(0));
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// }
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// }
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GpVar cond_ok;
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if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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GpVar cr(c.newGpVar());
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c.mov(cr, e.cr_value(i.XL.BI >> 2));
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c.and_(cr, imm(1 << (i.XL.BI & 3)));
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c.test(cr, imm(0));
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cond_ok = c.newGpVar();
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if (XESELECTBITS(i.XL.BO, 3, 3)) {
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c.setne(cond_ok);
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} else {
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c.sete(cond_ok);
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}
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}
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// // We do a bit of optimization here to make the llvm assembly easier to read.
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// jit_value_t ok = NULL;
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// if (cond_ok) {
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// ok = cond_ok;
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// }
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// We do a bit of optimization here to make the llvm assembly easier to read.
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GpVar* ok = NULL;
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if (cond_ok.getId() != kInvalidValue) {
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ok = &cond_ok;
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}
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// if (XeEmitBranchTo(e, c, "bcctrx", i.address, i.XL.LK, ok)) {
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// return 1;
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// }
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if (XeEmitBranchTo(e, c, "bcctrx", i.address, i.XL.LK, ok)) {
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return 1;
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}
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return 0;
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}
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@@ -318,54 +333,62 @@ XEEMITTER(bclrx, 0x4C000020, XL )(X64Emitter& e, X86Compiler& c, InstrDat
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// 01234 (docs)
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// 43210 (real)
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// // TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// // The docs say always, though...
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// if (i.XL.LK) {
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// e.update_lr_value(e.get_uint64(i.address + 4));
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// }
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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if (i.XL.LK) {
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e.update_lr_value(imm(i.address + 4));
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}
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// jit_value_t ctr_ok = NULL;
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// if (XESELECTBITS(i.XL.BO, 2, 2)) {
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// // Ignore ctr.
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// } else {
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// // Decrement counter.
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// jit_value_t ctr = e.ctr_value();
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// ctr = jit_insn_sub(f, ctr, e.get_int64(1));
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GpVar ctr_ok;
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if (XESELECTBITS(i.XL.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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GpVar ctr(c.newGpVar());
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c.mov(ctr, e.ctr_value());
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c.dec(ctr);
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e.update_ctr_value(ctr);
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// // Ctr check.
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// if (XESELECTBITS(i.XL.BO, 1, 1)) {
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// ctr_ok = jit_insn_eq(f, ctr, e.get_int64(0));
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// } else {
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// ctr_ok = jit_insn_ne(f, ctr, e.get_int64(0));
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// }
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// }
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// Ctr check.
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c.test(ctr, imm(0));
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ctr_ok = c.newGpVar();
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if (XESELECTBITS(i.XL.BO, 1, 1)) {
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c.sete(ctr_ok);
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} else {
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c.setne(ctr_ok);
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}
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}
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// jit_value_t cond_ok = NULL;
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// if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// // Ignore cond.
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// } else {
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// jit_value_t cr = e.cr_value(i.XL.BI >> 2);
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// cr = jit_insn_and(f, cr, e.get_uint32(1 << (i.XL.BI & 3)));
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// if (XESELECTBITS(i.XL.BO, 3, 3)) {
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// cond_ok = jit_insn_ne(f, cr, e.get_int64(0));
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// } else {
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// cond_ok = jit_insn_eq(f, cr, e.get_int64(0));
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// }
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// }
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GpVar cond_ok;
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if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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GpVar cr(c.newGpVar());
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c.mov(cr, e.cr_value(i.XL.BI >> 2));
|
||||
c.and_(cr, imm(1 << (i.XL.BI & 3)));
|
||||
c.test(cr, imm(0));
|
||||
cond_ok = c.newGpVar();
|
||||
if (XESELECTBITS(i.XL.BO, 3, 3)) {
|
||||
c.setne(cond_ok);
|
||||
} else {
|
||||
c.sete(cond_ok);
|
||||
}
|
||||
}
|
||||
|
||||
// // We do a bit of optimization here to make the llvm assembly easier to read.
|
||||
// jit_value_t ok = NULL;
|
||||
// if (ctr_ok && cond_ok) {
|
||||
// ok = jit_insn_and(f, ctr_ok, cond_ok);
|
||||
// } else if (ctr_ok) {
|
||||
// ok = ctr_ok;
|
||||
// } else if (cond_ok) {
|
||||
// ok = cond_ok;
|
||||
// }
|
||||
// We do a bit of optimization here to make the llvm assembly easier to read.
|
||||
GpVar* ok = NULL;
|
||||
if (ctr_ok.getId() != kInvalidValue && cond_ok.getId() != kInvalidValue) {
|
||||
c.and_(ctr_ok, cond_ok);
|
||||
ok = &ctr_ok;
|
||||
} else if (ctr_ok.getId() != kInvalidValue) {
|
||||
ok = &ctr_ok;
|
||||
} else if (cond_ok.getId() != kInvalidValue) {
|
||||
ok = &cond_ok;
|
||||
}
|
||||
|
||||
// if (XeEmitBranchTo(e, c, "bclrx", i.address, i.XL.LK, ok)) {
|
||||
// return 1;
|
||||
// }
|
||||
if (XeEmitBranchTo(e, c, "bclrx", i.address, i.XL.LK, ok)) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -480,35 +503,35 @@ int XeEmitTrap(X64Emitter& e, X86Compiler& c, InstrData& i,
|
||||
// // a < b
|
||||
// BasicBlock* bb = *(it++);
|
||||
// b.SetInsertPoint(bb);
|
||||
// jit_value_t cmp = b.CreateICmpSLT(va, vb);
|
||||
// GpVar cmp = b.CreateICmpSLT(va, vb);
|
||||
// b.CreateCondBr(cmp, trap_bb, *it);
|
||||
// }
|
||||
// if (TO & (1 << 3)) {
|
||||
// // a > b
|
||||
// BasicBlock* bb = *(it++);
|
||||
// b.SetInsertPoint(bb);
|
||||
// jit_value_t cmp = b.CreateICmpSGT(va, vb);
|
||||
// GpVar cmp = b.CreateICmpSGT(va, vb);
|
||||
// b.CreateCondBr(cmp, trap_bb, *it);
|
||||
// }
|
||||
// if (TO & (1 << 2)) {
|
||||
// // a = b
|
||||
// BasicBlock* bb = *(it++);
|
||||
// b.SetInsertPoint(bb);
|
||||
// jit_value_t cmp = b.CreateICmpEQ(va, vb);
|
||||
// GpVar cmp = b.CreateICmpEQ(va, vb);
|
||||
// b.CreateCondBr(cmp, trap_bb, *it);
|
||||
// }
|
||||
// if (TO & (1 << 1)) {
|
||||
// // a <u b
|
||||
// BasicBlock* bb = *(it++);
|
||||
// b.SetInsertPoint(bb);
|
||||
// jit_value_t cmp = b.CreateICmpULT(va, vb);
|
||||
// GpVar cmp = b.CreateICmpULT(va, vb);
|
||||
// b.CreateCondBr(cmp, trap_bb, *it);
|
||||
// }
|
||||
// if (TO & (1 << 0)) {
|
||||
// // a >u b
|
||||
// BasicBlock* bb = *(it++);
|
||||
// b.SetInsertPoint(bb);
|
||||
// jit_value_t cmp = b.CreateICmpUGT(va, vb);
|
||||
// GpVar cmp = b.CreateICmpUGT(va, vb);
|
||||
// b.CreateCondBr(cmp, trap_bb, *it);
|
||||
// }
|
||||
|
||||
|
||||
Reference in New Issue
Block a user