rldicl/rldicr tests.

src/alloy/frontend/ppc/test/bin/instr_rldicl.dis

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+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_rldicl.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_rldicl_1>:
+  100000:	78 83 c0 00 	rotldi  r3,r4,24
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_rldicl_2>:
+  100008:	78 83 c2 00 	rldicl  r3,r4,24,8
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_rldicl_3>:
+  100010:	78 83 c7 e0 	rldicl  r3,r4,24,63
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_rldicl_4>:
+  100018:	78 83 00 00 	rotldi  r3,r4,0
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_rldicl_5>:
+  100020:	78 83 07 e0 	clrldi  r3,r4,63
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_rldicl_6>:
+  100028:	78 83 02 00 	clrldi  r3,r4,8
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_rldicl_7>:
+  100030:	78 83 f8 02 	rotldi  r3,r4,63
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_rldicl_8>:
+  100038:	78 83 ff e2 	rldicl  r3,r4,63,63
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_rldicl_9>:
+  100040:	78 83 f8 00 	rotldi  r3,r4,31
+  100044:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_rldicl.map

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+0000000000000000 t test_rldicl_1
+0000000000000008 t test_rldicl_2
+0000000000000010 t test_rldicl_3
+0000000000000018 t test_rldicl_4
+0000000000000020 t test_rldicl_5
+0000000000000028 t test_rldicl_6
+0000000000000030 t test_rldicl_7
+0000000000000038 t test_rldicl_8
+0000000000000040 t test_rldicl_9

src/alloy/frontend/ppc/test/bin/instr_rldicr.dis

@@ -0,0 +1,41 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_rldicr.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_rldicr_1>:
+  100000:	78 83 c0 04 	rldicr  r3,r4,24,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_rldicr_2>:
+  100008:	78 83 c2 04 	rldicr  r3,r4,24,8
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_rldicr_3>:
+  100010:	78 83 c7 e4 	rldicr  r3,r4,24,63
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_rldicr_4>:
+  100018:	78 83 00 04 	rldicr  r3,r4,0,0
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_rldicr_5>:
+  100020:	78 83 07 e4 	rldicr  r3,r4,0,63
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_rldicr_6>:
+  100028:	78 83 02 04 	rldicr  r3,r4,0,8
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_rldicr_7>:
+  100030:	78 83 f8 06 	rldicr  r3,r4,63,0
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_rldicr_8>:
+  100038:	78 83 ff e6 	rldicr  r3,r4,63,63
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_rldicr_9>:
+  100040:	78 83 f8 04 	rldicr  r3,r4,31,0
+  100044:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_rldicr.map

@@ -0,0 +1,9 @@
+0000000000000000 t test_rldicr_1
+0000000000000008 t test_rldicr_2
+0000000000000010 t test_rldicr_3
+0000000000000018 t test_rldicr_4
+0000000000000020 t test_rldicr_5
+0000000000000028 t test_rldicr_6
+0000000000000030 t test_rldicr_7
+0000000000000038 t test_rldicr_8
+0000000000000040 t test_rldicr_9