add tests.
This commit is contained in:
Ben Vanik
BIN
src/alloy/frontend/ppc/test/bin/instr_addc.bin
Normal file
BIN
src/alloy/frontend/ppc/test/bin/instr_addc.bin
Normal file
Binary file not shown.
30
src/alloy/frontend/ppc/test/bin/instr_addc.dis
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30
src/alloy/frontend/ppc/test/bin/instr_addc.dis
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@@ -0,0 +1,30 @@
|
||||
|
||||
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_addc.o: file format elf64-powerpc
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0000000000100000 <test_addc_1>:
|
||||
100000: 7c 64 28 14 addc r3,r4,r5
|
||||
100004: 7c c0 01 14 adde r6,r0,r0
|
||||
100008: 4e 80 00 20 blr
|
||||
|
||||
000000000010000c <test_addc_2>:
|
||||
10000c: 7c 64 28 14 addc r3,r4,r5
|
||||
100010: 7c c0 01 14 adde r6,r0,r0
|
||||
100014: 4e 80 00 20 blr
|
||||
|
||||
0000000000100018 <test_addc_3>:
|
||||
100018: 7c 64 28 14 addc r3,r4,r5
|
||||
10001c: 7c c0 01 14 adde r6,r0,r0
|
||||
100020: 4e 80 00 20 blr
|
||||
|
||||
0000000000100024 <test_addc_4>:
|
||||
100024: 7c 64 28 14 addc r3,r4,r5
|
||||
100028: 7c c0 01 14 adde r6,r0,r0
|
||||
10002c: 4e 80 00 20 blr
|
||||
|
||||
0000000000100030 <test_addc_5>:
|
||||
100030: 7c 64 28 14 addc r3,r4,r5
|
||||
100034: 7c c0 01 14 adde r6,r0,r0
|
||||
100038: 4e 80 00 20 blr
|
||||
5
src/alloy/frontend/ppc/test/bin/instr_addc.map
Normal file
5
src/alloy/frontend/ppc/test/bin/instr_addc.map
Normal file
@@ -0,0 +1,5 @@
|
||||
0000000000000000 t test_addc_1
|
||||
000000000000000c t test_addc_2
|
||||
0000000000000018 t test_addc_3
|
||||
0000000000000024 t test_addc_4
|
||||
0000000000000030 t test_addc_5
|
||||
BIN
src/alloy/frontend/ppc/test/bin/instr_adde.bin
Normal file
BIN
src/alloy/frontend/ppc/test/bin/instr_adde.bin
Normal file
Binary file not shown.
70
src/alloy/frontend/ppc/test/bin/instr_adde.dis
Normal file
70
src/alloy/frontend/ppc/test/bin/instr_adde.dis
Normal file
@@ -0,0 +1,70 @@
|
||||
|
||||
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_adde.o: file format elf64-powerpc
|
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|
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|
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Disassembly of section .text:
|
||||
|
||||
0000000000100000 <test_adde_1>:
|
||||
100000: 7c 64 29 14 adde r3,r4,r5
|
||||
100004: 7c c0 01 14 adde r6,r0,r0
|
||||
100008: 4e 80 00 20 blr
|
||||
|
||||
000000000010000c <test_adde_2>:
|
||||
10000c: 7c 63 1a 78 xor r3,r3,r3
|
||||
100010: 7c 63 18 f8 not r3,r3
|
||||
100014: 30 63 00 01 addic r3,r3,1
|
||||
100018: 7c 64 29 14 adde r3,r4,r5
|
||||
10001c: 7c c0 01 14 adde r6,r0,r0
|
||||
100020: 4e 80 00 20 blr
|
||||
|
||||
0000000000100024 <test_adde_3>:
|
||||
100024: 7c 64 29 14 adde r3,r4,r5
|
||||
100028: 7c c0 01 14 adde r6,r0,r0
|
||||
10002c: 4e 80 00 20 blr
|
||||
|
||||
0000000000100030 <test_adde_4>:
|
||||
100030: 7c 63 1a 78 xor r3,r3,r3
|
||||
100034: 7c 63 18 f8 not r3,r3
|
||||
100038: 30 63 00 01 addic r3,r3,1
|
||||
10003c: 7c 64 29 14 adde r3,r4,r5
|
||||
100040: 7c c0 01 14 adde r6,r0,r0
|
||||
100044: 4e 80 00 20 blr
|
||||
|
||||
0000000000100048 <test_adde_5>:
|
||||
100048: 7c 64 29 14 adde r3,r4,r5
|
||||
10004c: 7c c0 01 14 adde r6,r0,r0
|
||||
100050: 4e 80 00 20 blr
|
||||
|
||||
0000000000100054 <test_adde_6>:
|
||||
100054: 7c 63 1a 78 xor r3,r3,r3
|
||||
100058: 7c 63 18 f8 not r3,r3
|
||||
10005c: 30 63 00 01 addic r3,r3,1
|
||||
100060: 7c 64 29 14 adde r3,r4,r5
|
||||
100064: 7c c0 01 14 adde r6,r0,r0
|
||||
100068: 4e 80 00 20 blr
|
||||
|
||||
000000000010006c <test_adde_7>:
|
||||
10006c: 7c 64 29 14 adde r3,r4,r5
|
||||
100070: 7c c0 01 14 adde r6,r0,r0
|
||||
100074: 4e 80 00 20 blr
|
||||
|
||||
0000000000100078 <test_adde_8>:
|
||||
100078: 7c 63 1a 78 xor r3,r3,r3
|
||||
10007c: 7c 63 18 f8 not r3,r3
|
||||
100080: 30 63 00 01 addic r3,r3,1
|
||||
100084: 7c 64 29 14 adde r3,r4,r5
|
||||
100088: 7c c0 01 14 adde r6,r0,r0
|
||||
10008c: 4e 80 00 20 blr
|
||||
|
||||
0000000000100090 <test_adde_9>:
|
||||
100090: 7c 64 29 14 adde r3,r4,r5
|
||||
100094: 7c c0 01 14 adde r6,r0,r0
|
||||
100098: 4e 80 00 20 blr
|
||||
|
||||
000000000010009c <test_adde_10>:
|
||||
10009c: 7c 63 1a 78 xor r3,r3,r3
|
||||
1000a0: 7c 63 18 f8 not r3,r3
|
||||
1000a4: 30 63 00 01 addic r3,r3,1
|
||||
1000a8: 7c 64 29 14 adde r3,r4,r5
|
||||
1000ac: 7c c0 01 14 adde r6,r0,r0
|
||||
1000b0: 4e 80 00 20 blr
|
||||
10
src/alloy/frontend/ppc/test/bin/instr_adde.map
Normal file
10
src/alloy/frontend/ppc/test/bin/instr_adde.map
Normal file
@@ -0,0 +1,10 @@
|
||||
0000000000000000 t test_adde_1
|
||||
000000000000000c t test_adde_2
|
||||
0000000000000024 t test_adde_3
|
||||
0000000000000030 t test_adde_4
|
||||
0000000000000048 t test_adde_5
|
||||
0000000000000054 t test_adde_6
|
||||
000000000000006c t test_adde_7
|
||||
0000000000000078 t test_adde_8
|
||||
0000000000000090 t test_adde_9
|
||||
000000000000009c t test_adde_10
|
||||
BIN
src/alloy/frontend/ppc/test/bin/instr_addme.bin
Normal file
BIN
src/alloy/frontend/ppc/test/bin/instr_addme.bin
Normal file
Binary file not shown.
57
src/alloy/frontend/ppc/test/bin/instr_addme.dis
Normal file
57
src/alloy/frontend/ppc/test/bin/instr_addme.dis
Normal file
@@ -0,0 +1,57 @@
|
||||
|
||||
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_addme.o: file format elf64-powerpc
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0000000000100000 <test_addme_1>:
|
||||
100000: 7c 64 01 d4 addme r3,r4
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||||
100004: 7c c0 01 14 adde r6,r0,r0
|
||||
100008: 4e 80 00 20 blr
|
||||
|
||||
000000000010000c <test_addme_2>:
|
||||
10000c: 7c 63 1a 78 xor r3,r3,r3
|
||||
100010: 7c 63 18 f8 not r3,r3
|
||||
100014: 30 63 00 01 addic r3,r3,1
|
||||
100018: 7c 64 01 d4 addme r3,r4
|
||||
10001c: 7c c0 01 14 adde r6,r0,r0
|
||||
100020: 4e 80 00 20 blr
|
||||
|
||||
0000000000100024 <test_addme_3>:
|
||||
100024: 7c 64 01 d4 addme r3,r4
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||||
100028: 7c c0 01 14 adde r6,r0,r0
|
||||
10002c: 4e 80 00 20 blr
|
||||
|
||||
0000000000100030 <test_addme_4>:
|
||||
100030: 7c 63 1a 78 xor r3,r3,r3
|
||||
100034: 7c 63 18 f8 not r3,r3
|
||||
100038: 30 63 00 01 addic r3,r3,1
|
||||
10003c: 7c 64 01 d4 addme r3,r4
|
||||
100040: 7c c0 01 14 adde r6,r0,r0
|
||||
100044: 4e 80 00 20 blr
|
||||
|
||||
0000000000100048 <test_addme_5>:
|
||||
100048: 7c 64 01 d4 addme r3,r4
|
||||
10004c: 7c c0 01 14 adde r6,r0,r0
|
||||
100050: 4e 80 00 20 blr
|
||||
|
||||
0000000000100054 <test_addme_6>:
|
||||
100054: 7c 63 1a 78 xor r3,r3,r3
|
||||
100058: 7c 63 18 f8 not r3,r3
|
||||
10005c: 30 63 00 01 addic r3,r3,1
|
||||
100060: 7c 64 01 d4 addme r3,r4
|
||||
100064: 7c c0 01 14 adde r6,r0,r0
|
||||
100068: 4e 80 00 20 blr
|
||||
|
||||
000000000010006c <test_addme_7>:
|
||||
10006c: 7c 64 01 d4 addme r3,r4
|
||||
100070: 7c c0 01 14 adde r6,r0,r0
|
||||
100074: 4e 80 00 20 blr
|
||||
|
||||
0000000000100078 <test_addme_8>:
|
||||
100078: 7c 63 1a 78 xor r3,r3,r3
|
||||
10007c: 7c 63 18 f8 not r3,r3
|
||||
100080: 30 63 00 01 addic r3,r3,1
|
||||
100084: 7c 64 01 d4 addme r3,r4
|
||||
100088: 7c c0 01 14 adde r6,r0,r0
|
||||
10008c: 4e 80 00 20 blr
|
||||
8
src/alloy/frontend/ppc/test/bin/instr_addme.map
Normal file
8
src/alloy/frontend/ppc/test/bin/instr_addme.map
Normal file
@@ -0,0 +1,8 @@
|
||||
0000000000000000 t test_addme_1
|
||||
000000000000000c t test_addme_2
|
||||
0000000000000024 t test_addme_3
|
||||
0000000000000030 t test_addme_4
|
||||
0000000000000048 t test_addme_5
|
||||
0000000000000054 t test_addme_6
|
||||
000000000000006c t test_addme_7
|
||||
0000000000000078 t test_addme_8
|
||||
BIN
src/alloy/frontend/ppc/test/bin/instr_addze.bin
Normal file
BIN
src/alloy/frontend/ppc/test/bin/instr_addze.bin
Normal file
Binary file not shown.
57
src/alloy/frontend/ppc/test/bin/instr_addze.dis
Normal file
57
src/alloy/frontend/ppc/test/bin/instr_addze.dis
Normal file
@@ -0,0 +1,57 @@
|
||||
|
||||
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_addze.o: file format elf64-powerpc
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0000000000100000 <test_addze_1>:
|
||||
100000: 7c 64 01 94 addze r3,r4
|
||||
100004: 7c c0 01 14 adde r6,r0,r0
|
||||
100008: 4e 80 00 20 blr
|
||||
|
||||
000000000010000c <test_addze_2>:
|
||||
10000c: 7c 63 1a 78 xor r3,r3,r3
|
||||
100010: 7c 63 18 f8 not r3,r3
|
||||
100014: 30 63 00 01 addic r3,r3,1
|
||||
100018: 7c 64 01 94 addze r3,r4
|
||||
10001c: 7c c0 01 14 adde r6,r0,r0
|
||||
100020: 4e 80 00 20 blr
|
||||
|
||||
0000000000100024 <test_addze_3>:
|
||||
100024: 7c 64 01 94 addze r3,r4
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||||
100028: 7c c0 01 14 adde r6,r0,r0
|
||||
10002c: 4e 80 00 20 blr
|
||||
|
||||
0000000000100030 <test_addze_4>:
|
||||
100030: 7c 63 1a 78 xor r3,r3,r3
|
||||
100034: 7c 63 18 f8 not r3,r3
|
||||
100038: 30 63 00 01 addic r3,r3,1
|
||||
10003c: 7c 64 01 94 addze r3,r4
|
||||
100040: 7c c0 01 14 adde r6,r0,r0
|
||||
100044: 4e 80 00 20 blr
|
||||
|
||||
0000000000100048 <test_addze_5>:
|
||||
100048: 7c 64 01 94 addze r3,r4
|
||||
10004c: 7c c0 01 14 adde r6,r0,r0
|
||||
100050: 4e 80 00 20 blr
|
||||
|
||||
0000000000100054 <test_addze_6>:
|
||||
100054: 7c 63 1a 78 xor r3,r3,r3
|
||||
100058: 7c 63 18 f8 not r3,r3
|
||||
10005c: 30 63 00 01 addic r3,r3,1
|
||||
100060: 7c 64 01 94 addze r3,r4
|
||||
100064: 7c c0 01 14 adde r6,r0,r0
|
||||
100068: 4e 80 00 20 blr
|
||||
|
||||
000000000010006c <test_addze_7>:
|
||||
10006c: 7c 64 01 94 addze r3,r4
|
||||
100070: 7c c0 01 14 adde r6,r0,r0
|
||||
100074: 4e 80 00 20 blr
|
||||
|
||||
0000000000100078 <test_addze_8>:
|
||||
100078: 7c 63 1a 78 xor r3,r3,r3
|
||||
10007c: 7c 63 18 f8 not r3,r3
|
||||
100080: 30 63 00 01 addic r3,r3,1
|
||||
100084: 7c 64 01 94 addze r3,r4
|
||||
100088: 7c c0 01 14 adde r6,r0,r0
|
||||
10008c: 4e 80 00 20 blr
|
||||
8
src/alloy/frontend/ppc/test/bin/instr_addze.map
Normal file
8
src/alloy/frontend/ppc/test/bin/instr_addze.map
Normal file
@@ -0,0 +1,8 @@
|
||||
0000000000000000 t test_addze_1
|
||||
000000000000000c t test_addze_2
|
||||
0000000000000024 t test_addze_3
|
||||
0000000000000030 t test_addze_4
|
||||
0000000000000048 t test_addze_5
|
||||
0000000000000054 t test_addze_6
|
||||
000000000000006c t test_addze_7
|
||||
0000000000000078 t test_addze_8
|
||||
54
src/alloy/frontend/ppc/test/instr_addc.s
Normal file
54
src/alloy/frontend/ppc/test/instr_addc.s
Normal file
@@ -0,0 +1,54 @@
|
||||
test_addc_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
#_ REGISTER_IN r5 2
|
||||
addc r3, r4, r5
|
||||
adde r6, r0, r0
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||||
blr
|
||||
#_ REGISTER_OUT r3 3
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r5 2
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addc_2:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0
|
||||
addc r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addc_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
addc r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addc_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 123
|
||||
addc r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x000000000000007A
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 123
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addc_5:
|
||||
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
|
||||
addc r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
|
||||
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
124
src/alloy/frontend/ppc/test/instr_adde.s
Normal file
124
src/alloy/frontend/ppc/test/instr_adde.s
Normal file
@@ -0,0 +1,124 @@
|
||||
test_adde_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
#_ REGISTER_IN r5 2
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 3
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r5 2
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_adde_2:
|
||||
#_ REGISTER_IN r4 1
|
||||
#_ REGISTER_IN r5 2
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 4
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r5 2
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_adde_3:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_adde_4:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_7:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 123
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x000000000000007A
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 123
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_8:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 123
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x000000000000007B
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 123
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_9:
|
||||
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
|
||||
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_10:
|
||||
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
83
src/alloy/frontend/ppc/test/instr_addme.s
Normal file
83
src/alloy/frontend/ppc/test/instr_addme.s
Normal file
@@ -0,0 +1,83 @@
|
||||
test_addme_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_2:
|
||||
#_ REGISTER_IN r4 1
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_3:
|
||||
#_ REGISTER_IN r4 12
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 11
|
||||
#_ REGISTER_OUT r4 12
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_4:
|
||||
#_ REGISTER_IN r4 12
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 12
|
||||
#_ REGISTER_OUT r4 12
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_7:
|
||||
#_ REGISTER_IN r4 0
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addme_8:
|
||||
#_ REGISTER_IN r4 0
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0
|
||||
#_ REGISTER_OUT r6 1
|
||||
83
src/alloy/frontend/ppc/test/instr_addze.s
Normal file
83
src/alloy/frontend/ppc/test/instr_addze.s
Normal file
@@ -0,0 +1,83 @@
|
||||
test_addze_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_2:
|
||||
#_ REGISTER_IN r4 1
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 2
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_3:
|
||||
#_ REGISTER_IN r4 12
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 12
|
||||
#_ REGISTER_OUT r4 12
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_4:
|
||||
#_ REGISTER_IN r4 12
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 13
|
||||
#_ REGISTER_OUT r4 12
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addze_7:
|
||||
#_ REGISTER_IN r4 0
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_8:
|
||||
#_ REGISTER_IN r4 0
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
Reference in New Issue
Block a user