[D3D12] 8/16bpp resolves, fixed16 RT exp bias, RT format documentation
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30
src/xenia/gpu/d3d12/shaders/texture_tile_8bpp.cs.hlsl
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30
src/xenia/gpu/d3d12/shaders/texture_tile_8bpp.cs.hlsl
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#include "texture_tile.hlsli"
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RWBuffer<uint> xe_texture_tile_dest : register(u0);
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[numthreads(8, 32, 1)]
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void main(uint3 xe_thread_id : SV_DispatchThreadID) {
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// 1 thread = 4 texels.
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uint2 texture_size = (xe_texture_tile_size >> uint2(0u, 16u)) & 0xFFFFu;
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uint2 texel_index = xe_thread_id.xy;
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texel_index.x <<= 2u;
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[branch] if (any(texel_index >= texture_size)) {
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return;
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}
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uint4 texels = (xe_texture_tile_source.Load(
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xe_texture_tile_host_base + texel_index.y * xe_texture_tile_host_pitch +
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texel_index.x).xxxx >> uint4(0u, 8u, 16u, 24u)) & 0xFFu;
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uint4 texel_addresses = xe_texture_tile_guest_base + XeTextureTiledOffset2D(
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texel_index, xe_texture_tile_endian_format_guest_pitch >> 9u, 0u);
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xe_texture_tile_dest[texel_addresses.x] = texels.x;
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bool3 texels_inside = uint3(1u, 2u, 3u) + texel_index.x < texture_size.x;
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[branch] if (texels_inside.x) {
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xe_texture_tile_dest[texel_addresses.y] = texels.y;
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[branch] if (texels_inside.y) {
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xe_texture_tile_dest[texel_addresses.z] = texels.z;
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[branch] if (texels_inside.z) {
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xe_texture_tile_dest[texel_addresses.w] = texels.w;
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}
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}
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}
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}
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