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[x64] Fix AVX-512 vctuxs NaN handling

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(using ordered comparison predicate)
This commit is contained in:
Herman S.
2026-02-12 21:39:53 +09:00
parent f95ebb9c55
commit 70c1092195
1 changed files with 5 additions and 6 deletions
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11
src/xenia/cpu/backend/x64/x64_seq_vector.cc
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@@ -101,13 +101,12 @@ struct VECTOR_CONVERT_F2I
if (i.instr->flags & ARITHMETIC_UNSIGNED) {
if (e.IsFeatureEnabled(kX64EmitAVX512Ortho)) {
Opmask mask = e.k1;
// Mask positive values and unordered values
// _CMP_NLT_UQ
e.vcmpps(mask, i.src1, e.GetXmmConstPtr(XMMZero), 0x15);
// Mask non-negative, non-NaN values (ordered, >= 0)
// _CMP_GE_OQ
e.vcmpps(mask, i.src1, e.GetXmmConstPtr(XMMZero), 0x1D);
// vcvttps2udq will saturate overflowing positive values and unordered
// values to UINT_MAX. Mask registers will write zero everywhere
// else (negative values)
// vcvttps2udq will saturate overflowing positive values to UINT_MAX.
// Zero-masking writes zero for negative values and NaN
e.vcvttps2udq(i.dest.reg() | mask | e.T_z, i.src1);
return;
}