From 70c1092195f96a484a04f55f12c288db1a5b398d Mon Sep 17 00:00:00 2001 From: "Herman S." <429230+has207@users.noreply.github.com> Date: Thu, 12 Feb 2026 21:39:53 +0900 Subject: [PATCH] [x64] Fix AVX-512 vctuxs NaN handling (using ordered comparison predicate) --- src/xenia/cpu/backend/x64/x64_seq_vector.cc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/xenia/cpu/backend/x64/x64_seq_vector.cc b/src/xenia/cpu/backend/x64/x64_seq_vector.cc index cc2f2cb46..1eacbbe39 100644 --- a/src/xenia/cpu/backend/x64/x64_seq_vector.cc +++ b/src/xenia/cpu/backend/x64/x64_seq_vector.cc @@ -101,13 +101,12 @@ struct VECTOR_CONVERT_F2I if (i.instr->flags & ARITHMETIC_UNSIGNED) { if (e.IsFeatureEnabled(kX64EmitAVX512Ortho)) { Opmask mask = e.k1; - // Mask positive values and unordered values - // _CMP_NLT_UQ - e.vcmpps(mask, i.src1, e.GetXmmConstPtr(XMMZero), 0x15); + // Mask non-negative, non-NaN values (ordered, >= 0) + // _CMP_GE_OQ + e.vcmpps(mask, i.src1, e.GetXmmConstPtr(XMMZero), 0x1D); - // vcvttps2udq will saturate overflowing positive values and unordered - // values to UINT_MAX. Mask registers will write zero everywhere - // else (negative values) + // vcvttps2udq will saturate overflowing positive values to UINT_MAX. + // Zero-masking writes zero for negative values and NaN e.vcvttps2udq(i.dest.reg() | mask | e.T_z, i.src1); return; }