[Testing] Add missing ALU instruction tests

src/xenia/cpu/ppc/testing/instr_addi.s

@@ -0,0 +1,73 @@
+test_addi_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  addi r3, r4, 0x500
+  blr
+  #_ REGISTER_OUT r3 0x0000000000001500
+  #_ REGISTER_OUT r4 0x0000000000001000
+
+test_addi_1_constant:
+  li r4, 0x1000
+  addi r3, r4, 0x500
+  blr
+  #_ REGISTER_OUT r3 0x0000000000001500
+  #_ REGISTER_OUT r4 0x0000000000001000
+
+test_addi_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  addi r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_addi_2_constant:
+  li r4, -1
+  addi r3, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_addi_3:
+  #_ REGISTER_IN r4 0x0000000000000100
+  addi r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 0x00000000000000FF
+  #_ REGISTER_OUT r4 0x0000000000000100
+
+test_addi_3_constant:
+  li r4, 0x100
+  addi r3, r4, -1
+  blr
+  #_ REGISTER_OUT r3 0x00000000000000FF
+  #_ REGISTER_OUT r4 0x0000000000000100
+
+test_addi_4:
+  #_ REGISTER_IN r0 0xDEADBEEFDEADBEEF
+  addi r3, r0, 0x1234
+  blr
+  #_ REGISTER_OUT r3 0x0000000000001234
+  #_ REGISTER_OUT r0 0xDEADBEEFDEADBEEF
+
+test_addi_4_constant:
+  lis r0, 0xDEAD
+  ori r0, r0, 0xBEEF
+  sldi r0, r0, 32
+  oris r0, r0, 0xDEAD
+  ori r0, r0, 0xBEEF
+  addi r3, r0, 0x1234
+  blr
+  #_ REGISTER_OUT r3 0x0000000000001234
+  #_ REGISTER_OUT r0 0xDEADBEEFDEADBEEF
+
+test_addi_5:
+  #_ REGISTER_IN r4 0x0000000000007FFF
+  addi r3, r4, 0x7FFF
+  blr
+  #_ REGISTER_OUT r3 0x000000000000FFFE
+  #_ REGISTER_OUT r4 0x0000000000007FFF
+
+test_addi_5_constant:
+  li r4, 0x7FFF
+  addi r3, r4, 0x7FFF
+  blr
+  #_ REGISTER_OUT r3 0x000000000000FFFE
+  #_ REGISTER_OUT r4 0x0000000000007FFF

src/xenia/cpu/ppc/testing/instr_nand.s

@@ -0,0 +1,99 @@
+test_nand_1:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_nand_1_constant:
+  li r4, -1
+  li r5, -1
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_nand_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_IN r5 0x7FFFFFFFFFFFFFFF
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000001
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r5 0x7FFFFFFFFFFFFFFF
+
+test_nand_2_constant:
+  li r4, -1
+  srdi r4, r4, 1
+  sldi r4, r4, 1
+  li r5, -1
+  srdi r5, r5, 1
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000001
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r5 0x7FFFFFFFFFFFFFFF
+
+test_nand_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0000000000000000
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_nand_3_constant:
+  li r4, 0
+  li r5, -1
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0000000000000000
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_nand_4:
+  #_ REGISTER_IN r4 0xFFFFFFFF00000000
+  #_ REGISTER_IN r5 0x00000000FFFFFFFF
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r5 0x00000000FFFFFFFF
+
+test_nand_4_constant:
+  li r4, -1
+  clrldi r4, r4, 32
+  sldi r4, r4, 32
+  li r5, -1
+  clrldi r5, r5, 32
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r5 0x00000000FFFFFFFF
+
+test_nand_5:
+  #_ REGISTER_IN r4 0xF0F0F0F0F0F0F0F0
+  #_ REGISTER_IN r5 0xF0F0F0F0F0F0F0F0
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0F0F0F0F0F0F0F0F
+  #_ REGISTER_OUT r4 0xF0F0F0F0F0F0F0F0
+  #_ REGISTER_OUT r5 0xF0F0F0F0F0F0F0F0
+
+test_nand_5_constant:
+  lis r4, 0xF0F0
+  ori r4, r4, 0xF0F0
+  sldi r4, r4, 32
+  oris r4, r4, 0xF0F0
+  ori r4, r4, 0xF0F0
+  mr r5, r4
+  nand r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0F0F0F0F0F0F0F0F
+  #_ REGISTER_OUT r4 0xF0F0F0F0F0F0F0F0
+  #_ REGISTER_OUT r5 0xF0F0F0F0F0F0F0F0

src/xenia/cpu/ppc/testing/instr_or.s

@@ -0,0 +1,107 @@
+test_or_1:
+  #_ REGISTER_IN r4 0xFFFFFFFF00000000
+  #_ REGISTER_IN r5 0x00000000FFFFFFFF
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r5 0x00000000FFFFFFFF
+
+test_or_1_constant:
+  li r4, -1
+  clrldi r4, r4, 32
+  sldi r4, r4, 32
+  li r5, -1
+  clrldi r5, r5, 32
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r5 0x00000000FFFFFFFF
+
+test_or_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_IN r5 0x7FFFFFFFFFFFFFFF
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r5 0x7FFFFFFFFFFFFFFF
+
+test_or_2_constant:
+  li r4, -1
+  srdi r4, r4, 1
+  sldi r4, r4, 1
+  li r5, -1
+  srdi r5, r5, 1
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r5 0x7FFFFFFFFFFFFFFF
+
+test_or_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0000000000000000
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_or_3_constant:
+  li r4, 0
+  li r5, -1
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0000000000000000
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_or_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x0000000000000000
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x123456789ABCDEF0
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_or_4_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  sldi r4, r4, 32
+  oris r4, r4, 0x9ABC
+  ori r4, r4, 0xDEF0
+  li r5, 0
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x123456789ABCDEF0
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_or_5:
+  #_ REGISTER_IN r4 0xFF00FF00FF00FF00
+  #_ REGISTER_IN r5 0x00FF00FF00FF00FF
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFF00FF00FF00FF00
+  #_ REGISTER_OUT r5 0x00FF00FF00FF00FF
+
+test_or_5_constant:
+  lis r4, 0xFF00
+  ori r4, r4, 0xFF00
+  sldi r4, r4, 32
+  oris r4, r4, 0xFF00
+  ori r4, r4, 0xFF00
+  lis r5, 0x00FF
+  ori r5, r5, 0x00FF
+  sldi r5, r5, 32
+  oris r5, r5, 0x00FF
+  ori r5, r5, 0x00FF
+  or r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFF00FF00FF00FF00
+  #_ REGISTER_OUT r5 0x00FF00FF00FF00FF

src/xenia/cpu/ppc/testing/instr_orc.s

@@ -0,0 +1,101 @@
+test_orc_1:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000000
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_orc_1_constant:
+  li r4, -1
+  li r5, 0
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0x0000000000000000
+
+test_orc_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_orc_2_constant:
+  li r4, -1
+  srdi r4, r4, 1
+  sldi r4, r4, 1
+  li r5, -1
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_orc_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000000000000
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_orc_3_constant:
+  li r4, 0
+  li r5, -1
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000000000000
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_orc_4:
+  #_ REGISTER_IN r4 0xFFFFFFFF00000000
+  #_ REGISTER_IN r5 0xFFFFFFFF00000000
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000000
+
+test_orc_4_constant:
+  li r4, -1
+  clrldi r4, r4, 32
+  sldi r4, r4, 32
+  mr r5, r4
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFF00000000
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000000
+
+test_orc_5:
+  #_ REGISTER_IN r4 0xF0F0F0F0F0F0F0F0
+  #_ REGISTER_IN r5 0x0F0F0F0F0F0F0F0F
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xF0F0F0F0F0F0F0F0
+  #_ REGISTER_OUT r4 0xF0F0F0F0F0F0F0F0
+  #_ REGISTER_OUT r5 0x0F0F0F0F0F0F0F0F
+
+test_orc_5_constant:
+  lis r4, 0xF0F0
+  ori r4, r4, 0xF0F0
+  sldi r4, r4, 32
+  oris r4, r4, 0xF0F0
+  ori r4, r4, 0xF0F0
+  lis r5, 0x0F0F
+  ori r5, r5, 0x0F0F
+  sldi r5, r5, 32
+  oris r5, r5, 0x0F0F
+  ori r5, r5, 0x0F0F
+  orc r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xF0F0F0F0F0F0F0F0
+  #_ REGISTER_OUT r4 0xF0F0F0F0F0F0F0F0
+  #_ REGISTER_OUT r5 0x0F0F0F0F0F0F0F0F

src/xenia/cpu/ppc/testing/instr_oris.s

@@ -0,0 +1,80 @@
+test_oris_1:
+  #_ REGISTER_IN r4 0xDEADBEEF00000000
+  oris r3, r4, 0xFEDC
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEFFEDC0000
+  #_ REGISTER_OUT r4 0xDEADBEEF00000000
+
+test_oris_1_constant:
+  lis r4, 0xDEAD
+  ori r4, r4, 0xBEEF
+  sldi r4, r4, 32
+  oris r3, r4, 0xFEDC
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEFFEDC0000
+  #_ REGISTER_OUT r4 0xDEADBEEF00000000
+
+test_oris_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  oris r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_oris_2_constant:
+  li r4, -1
+  oris r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_oris_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  oris r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFF0000
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_oris_3_constant:
+  li r4, 0
+  oris r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFF0000
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_oris_4:
+  #_ REGISTER_IN r4 0x123456789ABC0000
+  oris r3, r4, 0x0000
+  blr
+  #_ REGISTER_OUT r3 0x123456789ABC0000
+  #_ REGISTER_OUT r4 0x123456789ABC0000
+
+test_oris_4_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  sldi r4, r4, 32
+  oris r4, r4, 0x9ABC
+  oris r3, r4, 0x0000
+  blr
+  #_ REGISTER_OUT r3 0x123456789ABC0000
+  #_ REGISTER_OUT r4 0x123456789ABC0000
+
+test_oris_5:
+  #_ REGISTER_IN r4 0xFFFFFFFE0000AAAA
+  oris r3, r4, 0x5555
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFE5555AAAA
+  #_ REGISTER_OUT r4 0xFFFFFFFE0000AAAA
+
+test_oris_5_constant:
+  li r4, -1
+  srdi r4, r4, 1
+  sldi r4, r4, 1
+  clrldi r4, r4, 32
+  oris r4, r4, 0xAAAA
+  sldi r4, r4, 32
+  ori r4, r4, 0xAAAA
+  oris r3, r4, 0x5555
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFE5555AAAA
+  #_ REGISTER_OUT r4 0xFFFFFFFE0000AAAA

src/xenia/cpu/ppc/testing/instr_rldcl.s

@@ -0,0 +1,99 @@
+.macro make_full_test_constant dest, a, b, c, d
+  lis \dest, \a
+  ori \dest, \dest, \b
+  sldi \dest, \dest, 32
+  lis r3, \c
+  ori r3, r3, \d
+  clrldi r3, r3, 32
+  or \dest, \dest, r3
+.endm
+
+test_rldcl_1:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 24
+  rldcl r3, r4, r5, 0
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 24
+
+test_rldcl_1_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 24
+  rldcl r3, r4, r5, 0
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 24
+
+test_rldcl_2:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 24
+  rldcl r3, r4, r5, 8
+  blr
+  #_ REGISTER_OUT r3 0x0089abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 24
+
+test_rldcl_2_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 24
+  rldcl r3, r4, r5, 8
+  blr
+  #_ REGISTER_OUT r3 0x0089abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 24
+
+test_rldcl_3:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 0
+  rldcl r3, r4, r5, 0
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 0
+
+test_rldcl_3_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 0
+  rldcl r3, r4, r5, 0
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 0
+
+test_rldcl_4:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 63
+  rldcl r3, r4, r5, 0
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 63
+
+test_rldcl_4_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 63
+  rldcl r3, r4, r5, 0
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 63
+
+test_rldcl_5:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 32
+  rldcl r3, r4, r5, 32
+  blr
+  #_ REGISTER_OUT r3 0x0000000001234567
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 32
+
+test_rldcl_5_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 32
+  rldcl r3, r4, r5, 32
+  blr
+  #_ REGISTER_OUT r3 0x0000000001234567
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 32

src/xenia/cpu/ppc/testing/instr_rldcr.s

@@ -0,0 +1,99 @@
+.macro make_full_test_constant dest, a, b, c, d
+  lis \dest, \a
+  ori \dest, \dest, \b
+  sldi \dest, \dest, 32
+  lis r3, \c
+  ori r3, r3, \d
+  clrldi r3, r3, 32
+  or \dest, \dest, r3
+.endm
+
+test_rldcr_1:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 24
+  rldcr r3, r4, r5, 63
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 24
+
+test_rldcr_1_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 24
+  rldcr r3, r4, r5, 63
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012345
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 24
+
+test_rldcr_2:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 24
+  rldcr r3, r4, r5, 55
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012300
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 24
+
+test_rldcr_2_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 24
+  rldcr r3, r4, r5, 55
+  blr
+  #_ REGISTER_OUT r3 0x6789abcdef012300
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 24
+
+test_rldcr_3:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 0
+  rldcr r3, r4, r5, 63
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 0
+
+test_rldcr_3_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 0
+  rldcr r3, r4, r5, 63
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 0
+
+test_rldcr_4:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 63
+  rldcr r3, r4, r5, 63
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 63
+
+test_rldcr_4_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 63
+  rldcr r3, r4, r5, 63
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 63
+
+test_rldcr_5:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  #_ REGISTER_IN r5 32
+  rldcr r3, r4, r5, 31
+  blr
+  #_ REGISTER_OUT r3 0x89abcdef00000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 32
+
+test_rldcr_5_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  li r5, 32
+  rldcr r3, r4, r5, 31
+  blr
+  #_ REGISTER_OUT r3 0x89abcdef00000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+  #_ REGISTER_OUT r5 32

src/xenia/cpu/ppc/testing/instr_rldic.s

@@ -0,0 +1,79 @@
+.macro make_full_test_constant dest, a, b, c, d
+  lis \dest, \a
+  ori \dest, \dest, \b
+  sldi \dest, \dest, 32
+  lis r3, \c
+  ori r3, r3, \d
+  clrldi r3, r3, 32
+  or \dest, \dest, r3
+.endm
+
+test_rldic_1:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldic r3, r4, 24, 8
+  blr
+  #_ REGISTER_OUT r3 0x0089abcdef000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldic_1_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  rldic r3, r4, 24, 8
+  blr
+  #_ REGISTER_OUT r3 0x0089abcdef000000
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldic_2:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldic r3, r4, 0, 0
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldic_2_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  rldic r3, r4, 0, 0
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldic_3:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldic r3, r4, 32, 32
+  blr
+  #_ REGISTER_OUT r3 0x89abcdef01234567
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldic_3_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  rldic r3, r4, 32, 32
+  blr
+  #_ REGISTER_OUT r3 0x89abcdef01234567
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldic_4:
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldic r3, r4, 63, 1
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldic_4_constant:
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  rldic r3, r4, 63, 1
+  blr
+  #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldic_5:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  rldic r3, r4, 16, 48
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_rldic_5_constant:
+  li r4, -1
+  rldic r3, r4, 16, 48
+  blr
+  #_ REGISTER_OUT r3 0xffffffffffffffff
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF

src/xenia/cpu/ppc/testing/instr_rldimi.s

@@ -0,0 +1,92 @@
+.macro make_full_test_constant dest, a, b, c, d
+  lis \dest, \a
+  ori \dest, \dest, \b
+  sldi \dest, \dest, 32
+  lis r3, \c
+  ori r3, r3, \d
+  clrldi r3, r3, 32
+  or \dest, \dest, r3
+.endm
+
+test_rldimi_1:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldimi r3, r4, 0, 0
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldimi_1_constant:
+  li r3, -1
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  rldimi r3, r4, 0, 0
+  blr
+  #_ REGISTER_OUT r3 0x0123456789abcdef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldimi_2:
+  #_ REGISTER_IN r3 0x0000000000000000
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldimi r3, r4, 8, 48
+  blr
+  #_ REGISTER_OUT r3 0x000000000000ef00
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldimi_2_constant:
+  li r3, 0
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  rldimi r3, r4, 8, 48
+  blr
+  #_ REGISTER_OUT r3 0x0000000089abefef
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldimi_3:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  rldimi r3, r4, 32, 32
+  blr
+  #_ REGISTER_OUT r3 0x89ABCDEF01234567
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldimi_3_constant:
+  li r3, -1
+  make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
+  rldimi r3, r4, 32, 32
+  blr
+  #_ REGISTER_OUT r3 0x89ABCDEF01234567
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_rldimi_4:
+  #_ REGISTER_IN r3 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  rldimi r3, r4, 16, 32
+  blr
+  #_ REGISTER_OUT r3 0xAAAAAAAAFFFFAAAA
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+
+test_rldimi_4_constant:
+  li r3, -1
+  srdi r3, r3, 1
+  sldi r3, r3, 1
+  li r4, -1
+  clrldi r4, r4, 32
+  rldimi r3, r4, 16, 32
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+
+test_rldimi_5:
+  #_ REGISTER_IN r3 0x0000000000000000
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  rldimi r3, r4, 56, 0
+  blr
+  #_ REGISTER_OUT r3 0xFF00000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_rldimi_5_constant:
+  li r3, 0
+  li r4, -1
+  rldimi r3, r4, 56, 0
+  blr
+  #_ REGISTER_OUT r3 0xFF00000000000000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF

src/xenia/cpu/ppc/testing/instr_xor.s

@@ -0,0 +1,106 @@
+test_xor_1:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFF00000000
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000000
+
+test_xor_1_constant:
+  li r4, -1
+  li r5, -1
+  clrldi r5, r5, 32
+  sldi r5, r5, 32
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFF00000000
+
+test_xor_2:
+  #_ REGISTER_IN r4 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_IN r5 0x5555555555555555
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_OUT r5 0x5555555555555555
+
+test_xor_2_constant:
+  li r4, -1
+  srdi r4, r4, 1
+  sldi r4, r4, 1
+  li r5, -1
+  srdi r5, r5, 1
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000001
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r5 0x7FFFFFFFFFFFFFFF
+
+test_xor_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0000000000000000
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_xor_3_constant:
+  li r4, 0
+  li r5, -1
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0000000000000000
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_xor_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x123456789ABCDEF0
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x123456789ABCDEF0
+
+test_xor_4_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  sldi r4, r4, 32
+  oris r4, r4, 0x9ABC
+  ori r4, r4, 0xDEF0
+  mr r5, r4
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x123456789ABCDEF0
+
+test_xor_5:
+  #_ REGISTER_IN r4 0xFF00FF00FF00FF00
+  #_ REGISTER_IN r5 0x00FF00FF00FF00FF
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFF00FF00FF00FF00
+  #_ REGISTER_OUT r5 0x00FF00FF00FF00FF
+
+test_xor_5_constant:
+  lis r4, 0xFF00
+  ori r4, r4, 0xFF00
+  sldi r4, r4, 32
+  oris r4, r4, 0xFF00
+  ori r4, r4, 0xFF00
+  lis r5, 0x00FF
+  ori r5, r5, 0x00FF
+  sldi r5, r5, 32
+  oris r5, r5, 0x00FF
+  ori r5, r5, 0x00FF
+  xor r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFF00FF00FF00FF00
+  #_ REGISTER_OUT r5 0x00FF00FF00FF00FF

src/xenia/cpu/ppc/testing/instr_xori.s

@@ -0,0 +1,77 @@
+test_xori_1:
+  #_ REGISTER_IN r4 0xDEADBEEF00000000
+  xori r3, r4, 0xFEDC
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEF0000FEDC
+  #_ REGISTER_OUT r4 0xDEADBEEF00000000
+
+test_xori_1_constant:
+  lis r4, 0xDEAD
+  ori r4, r4, 0xBEEF
+  sldi r4, r4, 32
+  xori r3, r4, 0xFEDC
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEF0000FEDC
+  #_ REGISTER_OUT r4 0xDEADBEEF00000000
+
+test_xori_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  xori r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF0000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_xori_2_constant:
+  li r4, -1
+  xori r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF0000
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_xori_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  xori r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0x000000000000FFFF
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_xori_3_constant:
+  li r4, 0
+  xori r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0x000000000000FFFF
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_xori_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  xori r3, r4, 0x0000
+  blr
+  #_ REGISTER_OUT r3 0x123456789ABCDEF0
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+
+test_xori_4_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  sldi r4, r4, 32
+  oris r4, r4, 0x9ABC
+  ori r4, r4, 0xDEF0
+  xori r3, r4, 0x0000
+  blr
+  #_ REGISTER_OUT r3 0x123456789ABCDEF0
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+
+test_xori_5:
+  #_ REGISTER_IN r4 0xAAAAAAAAAAAAAAAA
+  xori r3, r4, 0x5555
+  blr
+  #_ REGISTER_OUT r3 0xAAAAAAAAAAAAFFFF
+  #_ REGISTER_OUT r4 0xAAAAAAAAAAAAAAAA
+
+test_xori_5_constant:
+  li r4, -1
+  srdi r4, r4, 1
+  sldi r4, r4, 1
+  xori r3, r4, 0x5555
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFAAAB
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFE

src/xenia/cpu/ppc/testing/instr_xoris.s

@@ -0,0 +1,76 @@
+test_xoris_1:
+  #_ REGISTER_IN r4 0xDEADBEEF00000000
+  xoris r3, r4, 0xFEDC
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEFFEDC0000
+  #_ REGISTER_OUT r4 0xDEADBEEF00000000
+
+test_xoris_1_constant:
+  lis r4, 0xDEAD
+  ori r4, r4, 0xBEEF
+  sldi r4, r4, 32
+  xoris r3, r4, 0xFEDC
+  blr
+  #_ REGISTER_OUT r3 0xDEADBEEFFEDC0000
+  #_ REGISTER_OUT r4 0xDEADBEEF00000000
+
+test_xoris_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  xoris r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF0000FFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_xoris_2_constant:
+  li r4, -1
+  xoris r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF0000FFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+
+test_xoris_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  xoris r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFF0000
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_xoris_3_constant:
+  li r4, 0
+  xoris r3, r4, 0xFFFF
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFF0000
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_xoris_4:
+  #_ REGISTER_IN r4 0x123456789ABC0000
+  xoris r3, r4, 0x0000
+  blr
+  #_ REGISTER_OUT r3 0x123456789ABC0000
+  #_ REGISTER_OUT r4 0x123456789ABC0000
+
+test_xoris_4_constant:
+  lis r4, 0x1234
+  ori r4, r4, 0x5678
+  sldi r4, r4, 32
+  oris r4, r4, 0x9ABC
+  xoris r3, r4, 0x0000
+  blr
+  #_ REGISTER_OUT r3 0x123456789ABC0000
+  #_ REGISTER_OUT r4 0x123456789ABC0000
+
+test_xoris_5:
+  #_ REGISTER_IN r4 0xAAAAAAAAAAAAAAAA
+  xoris r3, r4, 0x5555
+  blr
+  #_ REGISTER_OUT r3 0xAAAAAAAAFFFFAAAA
+  #_ REGISTER_OUT r4 0xAAAAAAAAAAAAAAAA
+
+test_xoris_5_constant:
+  li r4, -1
+  srdi r4, r4, 1
+  sldi r4, r4, 1
+  xoris r3, r4, 0x5555
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFAAAAFFFE
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFE