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[Lint] Added InsertBraces to linter to unify codebase to one standard

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This commit is contained in:
Gliniak
2026-05-08 18:47:25 +02:00
parent 2c68a2fc4b
commit 74f34818e7
39 changed files with 426 additions and 170 deletions
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4
src/xenia/cpu/backend/a64/a64_code_cache_posix.cc
View File

@@ -68,7 +68,9 @@ static size_t WriteULEB128(uint8_t* p, uint64_t value) {
do {
uint8_t byte = value & 0x7F;
value >>= 7;
if (value) byte |= 0x80;
if (value) {
byte |= 0x80;
}
p[count++] = byte;
} while (value);
return count;

8
src/xenia/cpu/backend/a64/a64_seq_util.h
View File

@@ -361,8 +361,12 @@ inline void PrepareVmxFpSources(A64Emitter& e, const T1& op1, const T2& op2,
int s1 = SrcVReg(e, op1, 0);
int s2 = SrcVReg(e, op2, 1);
// Copy to scratch v0/v1 so we don't modify live allocated registers.
if (s1 != 0) e.mov(VReg(0).b16, VReg(s1).b16);
if (s2 != 1) e.mov(VReg(1).b16, VReg(s2).b16);
if (s1 != 0) {
e.mov(VReg(0).b16, VReg(s1).b16);
}
if (s2 != 1) {
e.mov(VReg(1).b16, VReg(s2).b16);
}
// Flush denormal inputs in software only if FPCR.FZ doesn't handle it.
if (!e.IsFeatureEnabled(xe::arm64::kA64FZFlushesInputs)) {
FlushDenormals_V128(e, 0);

99
src/xenia/cpu/backend/a64/a64_seq_vector.cc
View File

@@ -271,30 +271,33 @@ struct VECTOR_ADD
switch (part_type) {
case INT8_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqadd(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.sqadd(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
} else {
e.add(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqadd(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.sqadd(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
} else {
e.add(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqadd(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.sqadd(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
} else {
e.add(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
@@ -328,30 +331,33 @@ struct VECTOR_SUB
switch (part_type) {
case INT8_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqsub(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.sqsub(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
} else {
e.sub(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqsub(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.sqsub(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
} else {
e.sub(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqsub(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.sqsub(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
} else {
e.sub(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
@@ -381,22 +387,25 @@ struct VECTOR_MAX
int d = i.dest.reg().getIdx();
switch (part_type) {
case INT8_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umax(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.smax(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umax(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.smax(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umax(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.smax(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
break;
default:
assert_unhandled_case(part_type);
@@ -441,22 +450,25 @@ struct VECTOR_MIN
int d = i.dest.reg().getIdx();
switch (part_type) {
case INT8_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umin(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.smin(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umin(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.smin(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umin(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.smin(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
break;
default:
assert_unhandled_case(part_type);
@@ -815,22 +827,25 @@ struct VECTOR_AVERAGE
// ARM64 has native rounding halving add: (a + b + 1) >> 1.
switch (part_type) {
case INT8_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.urhadd(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.srhadd(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.urhadd(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.srhadd(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.urhadd(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.srhadd(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
break;
default:
assert_unhandled_case(part_type);
@@ -1023,7 +1038,9 @@ struct SWIZZLE
uint8_t w3 = (swizzle_mask >> 6) & 0x3;
if (w0 == 0 && w1 == 1 && w2 == 2 && w3 == 3) {
// Identity.
if (d != s) e.mov(VReg(d).b16, VReg(s).b16);
if (d != s) {
e.mov(VReg(d).b16, VReg(s).b16);
}
} else if (w0 == w1 && w1 == w2 && w2 == w3) {
// Broadcast single lane.
e.dup(VReg(d).s4, VReg(s).s4[w0]);
@@ -1773,16 +1790,18 @@ struct UNPACK : Sequence<UNPACK, I<OPCODE_UNPACK, V128Op, V128Op>> {
e.rev32(VReg(d).h8, VReg(s).h8);
if (to_hi) {
// PPC high bytes are in the NEON low half after rev32.
if (is_unsigned)
if (is_unsigned) {
e.uxtl(VReg(d).h8, VReg(d).b8);
else
} else {
e.sxtl(VReg(d).h8, VReg(d).b8);
}
} else {
// PPC low bytes are in the NEON high half after rev32.
if (is_unsigned)
if (is_unsigned) {
e.uxtl2(VReg(d).h8, VReg(d).b16);
else
} else {
e.sxtl2(VReg(d).h8, VReg(d).b16);
}
}
}
static void Emit16_IN_32(A64Emitter& e, const EmitArgType& i,
@@ -1797,16 +1816,18 @@ struct UNPACK : Sequence<UNPACK, I<OPCODE_UNPACK, V128Op, V128Op>> {
// 32-bit pairs to fix the halfword ordering.
if (to_hi) {
// PPC high halfwords → NEON low half.
if (is_unsigned)
if (is_unsigned) {
e.uxtl(VReg(d).s4, VReg(s).h4);
else
} else {
e.sxtl(VReg(d).s4, VReg(s).h4);
}
} else {
// PPC low halfwords → NEON high half.
if (is_unsigned)
if (is_unsigned) {
e.uxtl2(VReg(d).s4, VReg(s).h8);
else
} else {
e.sxtl2(VReg(d).s4, VReg(s).h8);
}
}
e.rev64(VReg(d).s4, VReg(d).s4);
}

50
src/xenia/cpu/backend/a64/a64_sequences.cc
View File

@@ -606,10 +606,11 @@ static void EmitFmaWithPpcNan_F64(A64Emitter& e, DReg dest, DReg s1, DReg s2,
e.b(VS, nan_path);
// Fast path: no NaN input → hardware FMA.
if (is_sub)
if (is_sub) {
e.fnmsub(dest, s1, s2, s3);
else
} else {
e.fmadd(dest, s1, s2, s3);
}
// If result is NaN (0*inf or inf-inf), canonicalize to PPC default.
e.fcmp(dest, dest);
e.b(VC, done);
@@ -656,10 +657,11 @@ static void EmitFmaWithPpcNan_F32(A64Emitter& e, SReg dest, SReg s1, SReg s2,
e.fccmp(s3, s3, 0b0001, VC);
e.b(VS, nan_path);
if (is_sub)
if (is_sub) {
e.fnmsub(dest, s1, s2, s3);
else
} else {
e.fmadd(dest, s1, s2, s3);
}
e.fcmp(dest, dest);
e.b(VC, done);
e.mov(e.w0, static_cast<uint64_t>(0xFFC00000u));
@@ -1074,7 +1076,9 @@ struct ADD_CARRY_I16
e.add(e.w0, e.w0, i.src2);
}
if (i.src3.is_constant) {
if (i.src3.constant()) e.add(e.w0, e.w0, 1);
if (i.src3.constant()) {
e.add(e.w0, e.w0, 1);
}
} else {
e.add(e.w0, e.w0, i.src3);
}
@@ -1098,7 +1102,9 @@ struct ADD_CARRY_I32
e.add(e.w0, e.w0, i.src2);
}
if (i.src3.is_constant) {
if (i.src3.constant()) e.add(e.w0, e.w0, 1);
if (i.src3.constant()) {
e.add(e.w0, e.w0, 1);
}
} else {
e.add(e.w0, e.w0, i.src3);
}
@@ -1120,7 +1126,9 @@ struct ADD_CARRY_I64
e.add(e.x0, e.x0, i.src2);
}
if (i.src3.is_constant) {
if (i.src3.constant()) e.add(e.x0, e.x0, 1);
if (i.src3.constant()) {
e.add(e.x0, e.x0, 1);
}
} else {
// Zero-extend the I8 carry to 64-bit.
e.mov(e.w1, i.src3);
@@ -1920,7 +1928,9 @@ struct SHL_V128 : Sequence<SHL_V128, I<OPCODE_SHL, V128Op, V128Op, I8Op>> {
if (i.src2.is_constant) {
uint8_t sh = i.src2.constant() & 0x7;
if (sh == 0) {
if (d != s) e.mov(VReg(d).b16, VReg(s).b16);
if (d != s) {
e.mov(VReg(d).b16, VReg(s).b16);
}
return;
}
// Read carry before writing result (handles dest==src aliasing).
@@ -2045,7 +2055,9 @@ struct SHR_V128 : Sequence<SHR_V128, I<OPCODE_SHR, V128Op, V128Op, I8Op>> {
if (i.src2.is_constant) {
uint8_t sh = i.src2.constant() & 0x7;
if (sh == 0) {
if (d != s) e.mov(VReg(d).b16, VReg(s).b16);
if (d != s) {
e.mov(VReg(d).b16, VReg(s).b16);
}
return;
}
// Read carry before writing result (handles dest==src aliasing).
@@ -3972,7 +3984,9 @@ struct MUL_ADD_V128
// Flush s3 → v3, save to stack slot 2.
int s3 = SrcVReg(e, i.src3, 3);
if (s3 != 3) e.mov(VReg(3).b16, VReg(s3).b16);
if (s3 != 3) {
e.mov(VReg(3).b16, VReg(s3).b16);
}
if (!e.IsFeatureEnabled(xe::arm64::kA64FZFlushesInputs)) {
FlushDenormals_V128(e, 3, 0, 1);
}
@@ -4060,7 +4074,9 @@ struct MUL_SUB_V128
// Flush s3 → v3, save un-negated for NaN fixup.
int s3 = SrcVReg(e, i.src3, 3);
if (s3 != 3) e.mov(VReg(3).b16, VReg(s3).b16);
if (s3 != 3) {
e.mov(VReg(3).b16, VReg(s3).b16);
}
if (!e.IsFeatureEnabled(xe::arm64::kA64FZFlushesInputs)) {
FlushDenormals_V128(e, 3, 0, 1);
}
@@ -4493,7 +4509,9 @@ static uint32_t PpcVrsqrtefpLane(uint32_t bits) {
uint32_t mantissa = bits & 0x007FFFFF;
// -Inf → QNaN
if (bits == 0xFF800000u) return 0x7FC00000u;
if (bits == 0xFF800000u) {
return 0x7FC00000u;
}
// Denormal or zero (exp == 0)
if (biased_exp == 0) {
@@ -4512,7 +4530,9 @@ static uint32_t PpcVrsqrtefpLane(uint32_t bits) {
}
// Negative normal → QNaN
if (sign) return 0x7FC00000u;
if (sign) {
return 0x7FC00000u;
}
// Normal positive: table lookup + interpolation
int32_t unbiased_exp = (int32_t)biased_exp - 127;
@@ -4545,7 +4565,9 @@ static uint32_t PpcVrsqrtefpLane(uint32_t bits) {
}
// Rounding
if ((raw & 5) && (raw & 2)) raw += 4;
if ((raw & 5) && (raw & 2)) {
raw += 4;
}
// Assemble result
uint32_t res_exp = (uint32_t)((result_exp << 23) + 0x3F800000);

4
src/xenia/cpu/backend/code_cache_base.h
View File

@@ -375,7 +375,9 @@ class CodeCacheBase : public CodeCache {
size_t old_commit_mark, new_commit_mark;
do {
old_commit_mark = generated_code_commit_mark_;
if (high_mark <= old_commit_mark) break;
if (high_mark <= old_commit_mark) {
break;
}
new_commit_mark = old_commit_mark + 16_MiB;
if (generated_code_execute_base_ == generated_code_write_base_) {
xe::memory::AllocFixed(generated_code_execute_base_, new_commit_mark,

4
src/xenia/cpu/backend/x64/x64_code_cache_posix.cc
View File

@@ -55,7 +55,9 @@ static size_t WriteULEB128(uint8_t* p, uint64_t value) {
do {
uint8_t byte = value & 0x7F;
value >>= 7;
if (value) byte |= 0x80;
if (value) {
byte |= 0x80;
}
p[count++] = byte;
} while (value);
return count;

7
src/xenia/cpu/backend/x64/x64_emitter.cc
View File

@@ -865,12 +865,13 @@ void X64Emitter::SetReturnAddress(uint64_t value) {
}
Xbyak::Reg64 X64Emitter::GetNativeParam(uint32_t param) {
if (param == 0)
if (param == 0) {
return rdx;
else if (param == 1)
} else if (param == 1) {
return r8;
else if (param == 2)
} else if (param == 2) {
return r9;
}
assert_always();
return r9;

12
src/xenia/cpu/backend/x64/x64_sequences.cc
View File

@@ -957,8 +957,9 @@ struct COMPARE_EQ_I8
[](X64Emitter& e, const Reg8& src1, int32_t constant) {
if (constant == 0) {
e.test(src1, src1);
} else
} else {
e.cmp(src1, constant);
}
});
}
CompareEqDoSete(e, i.instr, i.dest);
@@ -976,8 +977,9 @@ struct COMPARE_EQ_I16
[](X64Emitter& e, const Reg16& src1, int32_t constant) {
if (constant == 0) {
e.test(src1, src1);
} else
} else {
e.cmp(src1, constant);
}
});
}
CompareEqDoSete(e, i.instr, i.dest);
@@ -995,8 +997,9 @@ struct COMPARE_EQ_I32
[](X64Emitter& e, const Reg32& src1, int32_t constant) {
if (constant == 0) {
e.test(src1, src1);
} else
} else {
e.cmp(src1, constant);
}
});
}
CompareEqDoSete(e, i.instr, i.dest);
@@ -1014,8 +1017,9 @@ struct COMPARE_EQ_I64
[](X64Emitter& e, const Reg64& src1, int32_t constant) {
if (constant == 0) {
e.test(src1, src1);
} else
} else {
e.cmp(src1, constant);
}
});
}
CompareEqDoSete(e, i.instr, i.dest);

4
src/xenia/cpu/compiler/passes/register_allocation_pass.cc
View File

@@ -510,7 +510,9 @@ void RegisterAllocationPass::SortUsageList(Value* value) {
for (int i = 0; i < insize; i++) {
psize++;
q = q->next;
if (!q) break;
if (!q) {
break;
}
}
// if q hasn't fallen off end, we have two lists to merge
int qsize = insize;

36
src/xenia/cpu/compiler/passes/simplification_pass.cc
View File

@@ -67,7 +67,9 @@ static bool IsScalarBasicCmp(Opcode op) {
}
static bool SameValueOrEqualConstant(hir::Value* x, hir::Value* y) {
if (x == y) return true;
if (x == y) {
return true;
}
if (x->IsConstant() && y->IsConstant()) {
return x->AsUint64() == y->AsUint64();
@@ -82,12 +84,18 @@ static bool CompareDefsHaveSameOpnds(hir::Value* cmp1, hir::Value* cmp2,
Opcode* out_r_op) {
auto df1 = cmp1->def;
auto df2 = cmp2->def;
if (!df1 || !df2) return false;
if (df1->src1.value != df2->src1.value) return false;
if (!df1 || !df2) {
return false;
}
if (df1->src1.value != df2->src1.value) {
return false;
}
Opcode lop = df1->opcode->num, rop = df2->opcode->num;
if (!IsScalarBasicCmp(lop) || !IsScalarBasicCmp(rop)) return false;
if (!IsScalarBasicCmp(lop) || !IsScalarBasicCmp(rop)) {
return false;
}
if (!SameValueOrEqualConstant(df1->src2.value, df2->src2.value)) {
return false;
@@ -101,7 +109,9 @@ static bool CompareDefsHaveSameOpnds(hir::Value* cmp1, hir::Value* cmp2,
}
bool SimplificationPass::CheckOr(hir::Instr* i, hir::HIRBuilder* builder) {
if (CheckOrXorZero(i)) return true;
if (CheckOrXorZero(i)) {
return true;
}
if (i->src1.value == i->src2.value) {
auto old1 = i->src1.value;
@@ -228,7 +238,9 @@ bool SimplificationPass::CheckXor(hir::Instr* i, hir::HIRBuilder* builder) {
uint64_t type_mask = GetScalarTypeMask(i->dest->type);
if (!constant_value) return false;
if (!constant_value) {
return false;
}
if (constant_value->AsUint64() == type_mask) {
i->Replace(&OPCODE_NOT_info, 0);
@@ -729,7 +741,9 @@ bool SimplificationPass::CheckSelect(hir::Instr* i, hir::HIRBuilder* builder) {
bool SimplificationPass::CheckScalarConstCmp(hir::Instr* i,
hir::HIRBuilder* builder) {
if (!IsScalarIntegralType(i->src1.value->type)) return false;
if (!IsScalarIntegralType(i->src1.value->type)) {
return false;
}
auto [constant_value, variable] = i->BinaryValueArrangeAsConstAndVar();
if (!constant_value) {
@@ -969,7 +983,9 @@ bool SimplificationPass::CheckSHRByConst(hir::Instr* i,
bool SimplificationPass::CheckSHR(hir::Instr* i, hir::HIRBuilder* builder) {
Value* shr_lhs = i->src1.value;
Value* shr_rhs = i->src2.value;
if (!shr_lhs || !shr_rhs) return false;
if (!shr_lhs || !shr_rhs) {
return false;
}
if (shr_rhs->IsConstant()) {
return CheckSHRByConst(i, builder, shr_lhs, shr_rhs->AsUint32());
}
@@ -1260,7 +1276,9 @@ bool SimplificationPass::SimplifyAndNot(hir::Instr* i,
Instr* def1 = src1->def;
Instr* def2 = src2->def;
if (!def1 || !def2) return false;
if (!def1 || !def2) {
return false;
}
// Bypass the NOT from an incoming operand and combine it into AND_NOT.
// If the original NOT does not have any further uses, then the

15
src/xenia/cpu/hir/instr.h
View File

@@ -94,15 +94,20 @@ class Instr {
TPredicate&& pred) {
auto src1_value = src1.value;
auto src2_value = src2.value;
if (!src1_value || !src2_value) return {nullptr, nullptr};
if (!src1_value || !src2_value) {
return {nullptr, nullptr};
}
if (!GetOpcodeInfo()) return {nullptr, nullptr}; // impossible!
if (!GetOpcodeInfo()) {
return {nullptr, nullptr}; // impossible!
}
// check if binary opcode taking two values. we dont care if the dest is a
// value
if (!IsOpcodeBinaryValue(GetOpcodeInfo()->signature))
if (!IsOpcodeBinaryValue(GetOpcodeInfo()->signature)) {
return {nullptr, nullptr};
}
if (pred(src1_value)) {
if (pred(src2_value)) {
@@ -142,7 +147,9 @@ if both are constant, return nullptr, nullptr
const OpcodeInfo* op_ptr) {
auto result = BinaryValueArrangeByDefiningOpcode(op_ptr);
if (!result.first) return result;
if (!result.first) {
return result;
}
if (!result.second->IsConstant()) {
return {nullptr, nullptr};
}

3
src/xenia/cpu/lzx.cc
View File

@@ -154,8 +154,9 @@ int lzxdelta_apply_patch(xe::xex2_delta_patch* patch, size_t patch_len,
int patch_sz = -4; // 0 byte patches need us to remove 4 byte from next
// patch addr because of patch_data field
if (cur_patch->compressed_len == 0 && cur_patch->uncompressed_len == 0 &&
cur_patch->new_addr == 0 && cur_patch->old_addr == 0)
cur_patch->new_addr == 0 && cur_patch->old_addr == 0) {
break;
}
switch (cur_patch->compressed_len) {
case 0: // fill with 0
std::memset((char*)dest + cur_patch->new_addr, 0,

20
src/xenia/cpu/ppc/ppc_opcode_disasm.cc
View File

@@ -22,7 +22,9 @@ namespace ppc {
void PadStringBuffer(StringBuffer* str, size_t base, size_t pad) {
size_t added_len = str->length() - base;
if (added_len < pad) str->AppendBytes(kSpaces, kNamePad - added_len);
if (added_len < pad) {
str->AppendBytes(kSpaces, kNamePad - added_len);
}
}
void PrintDisasm_bcx(const PPCDecodeData& d, StringBuffer* str) {
@@ -145,15 +147,23 @@ void PrintDisasm_bcx(const PPCDecodeData& d, StringBuffer* str) {
if (str_start == str->length()) {
// Default
str->Append("bc");
if (d.B.LK()) str->Append('l');
if (d.B.AA()) str->Append('a');
if (d.B.LK()) {
str->Append('l');
}
if (d.B.AA()) {
str->Append('a');
}
PadStringBuffer(str, str_start, kNamePad);
str->AppendFormat("{}", bo);
str->Append(", ");
str->AppendFormat("{}", bi);
} else {
if (d.B.LK()) str->Append('l');
if (d.B.AA()) str->Append('a');
if (d.B.LK()) {
str->Append('l');
}
if (d.B.AA()) {
str->Append('a');
}
if (sign_char > 0) {
str->Append('+');

23
src/xenia/cpu/ppc/ppc_translator.cc
View File

@@ -74,9 +74,13 @@ PPCTranslator::PPCTranslator(PPCFrontend* frontend) : frontend_(frontend) {
// Loops until no changes are made.
auto sap = std::make_unique<passes::ConditionalGroupPass>();
sap->AddPass(std::make_unique<passes::SimplificationPass>());
if (validate) sap->AddPass(std::make_unique<passes::ValidationPass>());
if (validate) {
sap->AddPass(std::make_unique<passes::ValidationPass>());
}
sap->AddPass(std::make_unique<passes::ConstantPropagationPass>());
if (validate) sap->AddPass(std::make_unique<passes::ValidationPass>());
if (validate) {
sap->AddPass(std::make_unique<passes::ValidationPass>());
}
compiler_->AddPass(std::move(sap));
if (backend->machine_info()->supports_extended_load_store) {
@@ -84,16 +88,21 @@ PPCTranslator::PPCTranslator(PPCFrontend* frontend) : frontend_(frontend) {
// These will save us a lot of HIR opcodes.
compiler_->AddPass(
std::make_unique<passes::MemorySequenceCombinationPass>());
if (validate)
if (validate) {
compiler_->AddPass(std::make_unique<passes::ValidationPass>());
}
}
compiler_->AddPass(std::make_unique<passes::SimplificationPass>());
if (validate) compiler_->AddPass(std::make_unique<passes::ValidationPass>());
if (validate) {
compiler_->AddPass(std::make_unique<passes::ValidationPass>());
}
// compiler_->AddPass(std::make_unique<passes::DeadStoreEliminationPass>());
// if (validate)
// compiler_->AddPass(std::make_unique<passes::ValidationPass>());
compiler_->AddPass(std::make_unique<passes::DeadCodeEliminationPass>());
if (validate) compiler_->AddPass(std::make_unique<passes::ValidationPass>());
if (validate) {
compiler_->AddPass(std::make_unique<passes::ValidationPass>());
}
//// Removes all unneeded variables. Try not to add new ones after this.
// compiler_->AddPass(new passes::ValueReductionPass());
@@ -105,7 +114,9 @@ PPCTranslator::PPCTranslator(PPCFrontend* frontend) : frontend_(frontend) {
// registers are assigned and ready to be emitted.
compiler_->AddPass(std::make_unique<passes::RegisterAllocationPass>(
backend->machine_info()));
if (validate) compiler_->AddPass(std::make_unique<passes::ValidationPass>());
if (validate) {
compiler_->AddPass(std::make_unique<passes::ValidationPass>());
}
// Must come last. The HIR is not really HIR after this.
compiler_->AddPass(std::make_unique<passes::FinalizationPass>());

20
src/xenia/cpu/ppc/testing/ppc_testing_main.cc
View File

@@ -376,7 +376,9 @@ class TestRunner {
auto p = memory_->TranslateVirtual(address);
const char* c = bytes_str.c_str();
while (*c) {
while (*c == ' ') ++c;
while (*c == ' ') {
++c;
}
if (!*c) {
break;
}
@@ -425,7 +427,9 @@ class TestRunner {
StringBuffer expecteds;
StringBuffer actuals;
while (*c) {
while (*c == ' ') ++c;
while (*c == ' ') {
++c;
}
if (!*c) {
break;
}
@@ -728,7 +732,9 @@ bool RunTests(const std::vector<std::string>& test_names) {
suite_tests.push_back(&test_case);
}
}
if (suite_tests.empty()) continue;
if (suite_tests.empty()) {
continue;
}
++suite_index;
int pct =
@@ -753,7 +759,9 @@ bool RunTests(const std::vector<std::string>& test_names) {
// instance per thread (avoids shm name collisions between concurrent
// children).
unsigned int num_cores = std::thread::hardware_concurrency();
if (num_cores == 0) num_cores = 4;
if (num_cores == 0) {
num_cores = 4;
}
num_cores = std::max(1u, num_cores * 3 / 4);
fprintf(stderr, "Running tests in parallel using %u workers\n", num_cores);
@@ -795,7 +803,9 @@ bool RunTests(const std::vector<std::string>& test_names) {
while (true) {
size_t idx = test_index.fetch_add(1);
if (idx >= all_tests.size()) break;
if (idx >= all_tests.size()) {
break;
}
auto& [test_suite, test_case] = all_tests[idx];
int local_failed = 0;

8
src/xenia/cpu/testing/f32_test.cc
View File

@@ -19,8 +19,12 @@ using xe::cpu::ppc::PPCContext;
// Helper for floating-point comparison with epsilon
static bool ApproxEqual(double a, double b, double epsilon = 1e-6) {
if (std::isnan(a) && std::isnan(b)) return true;
if (std::isinf(a) && std::isinf(b)) return (a > 0) == (b > 0);
if (std::isnan(a) && std::isnan(b)) {
return true;
}
if (std::isinf(a) && std::isinf(b)) {
return (a > 0) == (b > 0);
}
return std::abs(a - b) <= epsilon * std::max(std::abs(a), std::abs(b));
}

8
src/xenia/cpu/testing/misc_opcode_test.cc
View File

@@ -580,7 +580,9 @@ TEST_CASE("LOAD_VECTOR_LEFT", "[memory]") {
uint32_t aligned_addr = (guest_addr + 15) & ~15u;
auto* host_ptr =
reinterpret_cast<uint8_t*>(test.memory->TranslateVirtual(aligned_addr));
for (int i = 0; i < 16; ++i) host_ptr[i] = static_cast<uint8_t>(0x10 + i);
for (int i = 0; i < 16; ++i) {
host_ptr[i] = static_cast<uint8_t>(0x10 + i);
}
// LVL at aligned address — should load data (not crash).
test.Run([&](PPCContext* ctx) { ctx->r[4] = aligned_addr; },
@@ -604,7 +606,9 @@ TEST_CASE("LOAD_VECTOR_RIGHT", "[memory]") {
uint32_t aligned_addr = (guest_addr + 15) & ~15u;
auto* host_ptr =
reinterpret_cast<uint8_t*>(test.memory->TranslateVirtual(aligned_addr));
for (int i = 0; i < 16; ++i) host_ptr[i] = static_cast<uint8_t>(0x20 + i);
for (int i = 0; i < 16; ++i) {
host_ptr[i] = static_cast<uint8_t>(0x20 + i);
}
// LVR at aligned address returns zero (no bytes before alignment boundary).
test.Run([&](PPCContext* ctx) { ctx->r[4] = aligned_addr; },

3
src/xenia/cpu/xex_module.cc
View File

@@ -941,8 +941,9 @@ bool XexModule::Load(const std::string_view name, const std::string_view path,
// back to xex_security_info otherwise
base_address_ = xex_security_info()->load_address;
xe::be<uint32_t>* base_addr_opt = nullptr;
if (GetOptHeader(XEX_HEADER_IMAGE_BASE_ADDRESS, &base_addr_opt))
if (GetOptHeader(XEX_HEADER_IMAGE_BASE_ADDRESS, &base_addr_opt)) {
base_address_ = *base_addr_opt;
}
// Setup debug info.
name_ = name;