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[Lint] Added InsertBraces to linter to unify codebase to one standard

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This commit is contained in:
Gliniak
2026-05-08 18:47:25 +02:00
parent 2c68a2fc4b
commit 74f34818e7
39 changed files with 426 additions and 170 deletions
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4
src/xenia/cpu/backend/a64/a64_code_cache_posix.cc
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@@ -68,7 +68,9 @@ static size_t WriteULEB128(uint8_t* p, uint64_t value) {
do {
uint8_t byte = value & 0x7F;
value >>= 7;
if (value) byte |= 0x80;
if (value) {
byte |= 0x80;
}
p[count++] = byte;
} while (value);
return count;

8
src/xenia/cpu/backend/a64/a64_seq_util.h
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@@ -361,8 +361,12 @@ inline void PrepareVmxFpSources(A64Emitter& e, const T1& op1, const T2& op2,
int s1 = SrcVReg(e, op1, 0);
int s2 = SrcVReg(e, op2, 1);
// Copy to scratch v0/v1 so we don't modify live allocated registers.
if (s1 != 0) e.mov(VReg(0).b16, VReg(s1).b16);
if (s2 != 1) e.mov(VReg(1).b16, VReg(s2).b16);
if (s1 != 0) {
e.mov(VReg(0).b16, VReg(s1).b16);
}
if (s2 != 1) {
e.mov(VReg(1).b16, VReg(s2).b16);
}
// Flush denormal inputs in software only if FPCR.FZ doesn't handle it.
if (!e.IsFeatureEnabled(xe::arm64::kA64FZFlushesInputs)) {
FlushDenormals_V128(e, 0);

99
src/xenia/cpu/backend/a64/a64_seq_vector.cc
View File

@@ -271,30 +271,33 @@ struct VECTOR_ADD
switch (part_type) {
case INT8_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqadd(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.sqadd(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
} else {
e.add(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqadd(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.sqadd(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
} else {
e.add(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqadd(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.sqadd(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
} else {
e.add(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
@@ -328,30 +331,33 @@ struct VECTOR_SUB
switch (part_type) {
case INT8_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqsub(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.sqsub(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
} else {
e.sub(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqsub(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.sqsub(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
} else {
e.sub(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (saturate) {
if (is_unsigned)
if (is_unsigned) {
e.uqsub(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.sqsub(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
} else {
e.sub(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
@@ -381,22 +387,25 @@ struct VECTOR_MAX
int d = i.dest.reg().getIdx();
switch (part_type) {
case INT8_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umax(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.smax(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umax(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.smax(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umax(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.smax(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
break;
default:
assert_unhandled_case(part_type);
@@ -441,22 +450,25 @@ struct VECTOR_MIN
int d = i.dest.reg().getIdx();
switch (part_type) {
case INT8_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umin(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.smin(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umin(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.smin(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.umin(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.smin(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
break;
default:
assert_unhandled_case(part_type);
@@ -815,22 +827,25 @@ struct VECTOR_AVERAGE
// ARM64 has native rounding halving add: (a + b + 1) >> 1.
switch (part_type) {
case INT8_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.urhadd(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
else
} else {
e.srhadd(VReg(d).b16, VReg(s1).b16, VReg(s2).b16);
}
break;
case INT16_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.urhadd(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
else
} else {
e.srhadd(VReg(d).h8, VReg(s1).h8, VReg(s2).h8);
}
break;
case INT32_TYPE:
if (is_unsigned)
if (is_unsigned) {
e.urhadd(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
else
} else {
e.srhadd(VReg(d).s4, VReg(s1).s4, VReg(s2).s4);
}
break;
default:
assert_unhandled_case(part_type);
@@ -1023,7 +1038,9 @@ struct SWIZZLE
uint8_t w3 = (swizzle_mask >> 6) & 0x3;
if (w0 == 0 && w1 == 1 && w2 == 2 && w3 == 3) {
// Identity.
if (d != s) e.mov(VReg(d).b16, VReg(s).b16);
if (d != s) {
e.mov(VReg(d).b16, VReg(s).b16);
}
} else if (w0 == w1 && w1 == w2 && w2 == w3) {
// Broadcast single lane.
e.dup(VReg(d).s4, VReg(s).s4[w0]);
@@ -1773,16 +1790,18 @@ struct UNPACK : Sequence<UNPACK, I<OPCODE_UNPACK, V128Op, V128Op>> {
e.rev32(VReg(d).h8, VReg(s).h8);
if (to_hi) {
// PPC high bytes are in the NEON low half after rev32.
if (is_unsigned)
if (is_unsigned) {
e.uxtl(VReg(d).h8, VReg(d).b8);
else
} else {
e.sxtl(VReg(d).h8, VReg(d).b8);
}
} else {
// PPC low bytes are in the NEON high half after rev32.
if (is_unsigned)
if (is_unsigned) {
e.uxtl2(VReg(d).h8, VReg(d).b16);
else
} else {
e.sxtl2(VReg(d).h8, VReg(d).b16);
}
}
}
static void Emit16_IN_32(A64Emitter& e, const EmitArgType& i,
@@ -1797,16 +1816,18 @@ struct UNPACK : Sequence<UNPACK, I<OPCODE_UNPACK, V128Op, V128Op>> {
// 32-bit pairs to fix the halfword ordering.
if (to_hi) {
// PPC high halfwords → NEON low half.
if (is_unsigned)
if (is_unsigned) {
e.uxtl(VReg(d).s4, VReg(s).h4);
else
} else {
e.sxtl(VReg(d).s4, VReg(s).h4);
}
} else {
// PPC low halfwords → NEON high half.
if (is_unsigned)
if (is_unsigned) {
e.uxtl2(VReg(d).s4, VReg(s).h8);
else
} else {
e.sxtl2(VReg(d).s4, VReg(s).h8);
}
}
e.rev64(VReg(d).s4, VReg(d).s4);
}

50
src/xenia/cpu/backend/a64/a64_sequences.cc
View File

@@ -606,10 +606,11 @@ static void EmitFmaWithPpcNan_F64(A64Emitter& e, DReg dest, DReg s1, DReg s2,
e.b(VS, nan_path);
// Fast path: no NaN input → hardware FMA.
if (is_sub)
if (is_sub) {
e.fnmsub(dest, s1, s2, s3);
else
} else {
e.fmadd(dest, s1, s2, s3);
}
// If result is NaN (0*inf or inf-inf), canonicalize to PPC default.
e.fcmp(dest, dest);
e.b(VC, done);
@@ -656,10 +657,11 @@ static void EmitFmaWithPpcNan_F32(A64Emitter& e, SReg dest, SReg s1, SReg s2,
e.fccmp(s3, s3, 0b0001, VC);
e.b(VS, nan_path);
if (is_sub)
if (is_sub) {
e.fnmsub(dest, s1, s2, s3);
else
} else {
e.fmadd(dest, s1, s2, s3);
}
e.fcmp(dest, dest);
e.b(VC, done);
e.mov(e.w0, static_cast<uint64_t>(0xFFC00000u));
@@ -1074,7 +1076,9 @@ struct ADD_CARRY_I16
e.add(e.w0, e.w0, i.src2);
}
if (i.src3.is_constant) {
if (i.src3.constant()) e.add(e.w0, e.w0, 1);
if (i.src3.constant()) {
e.add(e.w0, e.w0, 1);
}
} else {
e.add(e.w0, e.w0, i.src3);
}
@@ -1098,7 +1102,9 @@ struct ADD_CARRY_I32
e.add(e.w0, e.w0, i.src2);
}
if (i.src3.is_constant) {
if (i.src3.constant()) e.add(e.w0, e.w0, 1);
if (i.src3.constant()) {
e.add(e.w0, e.w0, 1);
}
} else {
e.add(e.w0, e.w0, i.src3);
}
@@ -1120,7 +1126,9 @@ struct ADD_CARRY_I64
e.add(e.x0, e.x0, i.src2);
}
if (i.src3.is_constant) {
if (i.src3.constant()) e.add(e.x0, e.x0, 1);
if (i.src3.constant()) {
e.add(e.x0, e.x0, 1);
}
} else {
// Zero-extend the I8 carry to 64-bit.
e.mov(e.w1, i.src3);
@@ -1920,7 +1928,9 @@ struct SHL_V128 : Sequence<SHL_V128, I<OPCODE_SHL, V128Op, V128Op, I8Op>> {
if (i.src2.is_constant) {
uint8_t sh = i.src2.constant() & 0x7;
if (sh == 0) {
if (d != s) e.mov(VReg(d).b16, VReg(s).b16);
if (d != s) {
e.mov(VReg(d).b16, VReg(s).b16);
}
return;
}
// Read carry before writing result (handles dest==src aliasing).
@@ -2045,7 +2055,9 @@ struct SHR_V128 : Sequence<SHR_V128, I<OPCODE_SHR, V128Op, V128Op, I8Op>> {
if (i.src2.is_constant) {
uint8_t sh = i.src2.constant() & 0x7;
if (sh == 0) {
if (d != s) e.mov(VReg(d).b16, VReg(s).b16);
if (d != s) {
e.mov(VReg(d).b16, VReg(s).b16);
}
return;
}
// Read carry before writing result (handles dest==src aliasing).
@@ -3972,7 +3984,9 @@ struct MUL_ADD_V128
// Flush s3 → v3, save to stack slot 2.
int s3 = SrcVReg(e, i.src3, 3);
if (s3 != 3) e.mov(VReg(3).b16, VReg(s3).b16);
if (s3 != 3) {
e.mov(VReg(3).b16, VReg(s3).b16);
}
if (!e.IsFeatureEnabled(xe::arm64::kA64FZFlushesInputs)) {
FlushDenormals_V128(e, 3, 0, 1);
}
@@ -4060,7 +4074,9 @@ struct MUL_SUB_V128
// Flush s3 → v3, save un-negated for NaN fixup.
int s3 = SrcVReg(e, i.src3, 3);
if (s3 != 3) e.mov(VReg(3).b16, VReg(s3).b16);
if (s3 != 3) {
e.mov(VReg(3).b16, VReg(s3).b16);
}
if (!e.IsFeatureEnabled(xe::arm64::kA64FZFlushesInputs)) {
FlushDenormals_V128(e, 3, 0, 1);
}
@@ -4493,7 +4509,9 @@ static uint32_t PpcVrsqrtefpLane(uint32_t bits) {
uint32_t mantissa = bits & 0x007FFFFF;
// -Inf → QNaN
if (bits == 0xFF800000u) return 0x7FC00000u;
if (bits == 0xFF800000u) {
return 0x7FC00000u;
}
// Denormal or zero (exp == 0)
if (biased_exp == 0) {
@@ -4512,7 +4530,9 @@ static uint32_t PpcVrsqrtefpLane(uint32_t bits) {
}
// Negative normal → QNaN
if (sign) return 0x7FC00000u;
if (sign) {
return 0x7FC00000u;
}
// Normal positive: table lookup + interpolation
int32_t unbiased_exp = (int32_t)biased_exp - 127;
@@ -4545,7 +4565,9 @@ static uint32_t PpcVrsqrtefpLane(uint32_t bits) {
}
// Rounding
if ((raw & 5) && (raw & 2)) raw += 4;
if ((raw & 5) && (raw & 2)) {
raw += 4;
}
// Assemble result
uint32_t res_exp = (uint32_t)((result_exp << 23) + 0x3F800000);

4
src/xenia/cpu/backend/code_cache_base.h
View File

@@ -375,7 +375,9 @@ class CodeCacheBase : public CodeCache {
size_t old_commit_mark, new_commit_mark;
do {
old_commit_mark = generated_code_commit_mark_;
if (high_mark <= old_commit_mark) break;
if (high_mark <= old_commit_mark) {
break;
}
new_commit_mark = old_commit_mark + 16_MiB;
if (generated_code_execute_base_ == generated_code_write_base_) {
xe::memory::AllocFixed(generated_code_execute_base_, new_commit_mark,

4
src/xenia/cpu/backend/x64/x64_code_cache_posix.cc
View File

@@ -55,7 +55,9 @@ static size_t WriteULEB128(uint8_t* p, uint64_t value) {
do {
uint8_t byte = value & 0x7F;
value >>= 7;
if (value) byte |= 0x80;
if (value) {
byte |= 0x80;
}
p[count++] = byte;
} while (value);
return count;

7
src/xenia/cpu/backend/x64/x64_emitter.cc
View File

@@ -865,12 +865,13 @@ void X64Emitter::SetReturnAddress(uint64_t value) {
}
Xbyak::Reg64 X64Emitter::GetNativeParam(uint32_t param) {
if (param == 0)
if (param == 0) {
return rdx;
else if (param == 1)
} else if (param == 1) {
return r8;
else if (param == 2)
} else if (param == 2) {
return r9;
}
assert_always();
return r9;

12
src/xenia/cpu/backend/x64/x64_sequences.cc
View File

@@ -957,8 +957,9 @@ struct COMPARE_EQ_I8
[](X64Emitter& e, const Reg8& src1, int32_t constant) {
if (constant == 0) {
e.test(src1, src1);
} else
} else {
e.cmp(src1, constant);
}
});
}
CompareEqDoSete(e, i.instr, i.dest);
@@ -976,8 +977,9 @@ struct COMPARE_EQ_I16
[](X64Emitter& e, const Reg16& src1, int32_t constant) {
if (constant == 0) {
e.test(src1, src1);
} else
} else {
e.cmp(src1, constant);
}
});
}
CompareEqDoSete(e, i.instr, i.dest);
@@ -995,8 +997,9 @@ struct COMPARE_EQ_I32
[](X64Emitter& e, const Reg32& src1, int32_t constant) {
if (constant == 0) {
e.test(src1, src1);
} else
} else {
e.cmp(src1, constant);
}
});
}
CompareEqDoSete(e, i.instr, i.dest);
@@ -1014,8 +1017,9 @@ struct COMPARE_EQ_I64
[](X64Emitter& e, const Reg64& src1, int32_t constant) {
if (constant == 0) {
e.test(src1, src1);
} else
} else {
e.cmp(src1, constant);
}
});
}
CompareEqDoSete(e, i.instr, i.dest);