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Adding VECTOR_SUB for vsub*.

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This commit is contained in:
Ben Vanik
2014-08-05 14:03:49 -07:00
parent f149a23367
commit 75eb87f33d
7 changed files with 148 additions and 37 deletions
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40
src/alloy/backend/ivm/ivm_intcode.cc
View File

@@ -2735,6 +2735,12 @@ int Translate_SUB(TranslationContext& ctx, Instr* i) {
return DispatchToC(ctx, i, fns[i->dest->type]);
}
int Translate_VECTOR_SUB(TranslationContext& ctx, Instr* i) {
// TODO(benvanik): VECTOR_SUB in IVM.
assert_always();
return 1;
}
uint32_t IntCode_MUL_I8_I8(IntCodeState& ics, const IntCode* i) {
ics.rf[i->dest_reg].i8 = ics.rf[i->src1_reg].i8 * ics.rf[i->src2_reg].i8;
return IA_NEXT;
@@ -4200,23 +4206,23 @@ static const TranslateFn dispatch_table[] = {
Translate_VECTOR_COMPARE_UGT, Translate_VECTOR_COMPARE_UGE,
Translate_ADD, Translate_ADD_CARRY,
Translate_VECTOR_ADD, Translate_SUB,
Translate_MUL, Translate_MUL_HI,
Translate_DIV, Translate_MUL_ADD,
Translate_MUL_SUB, Translate_NEG,
Translate_ABS, Translate_SQRT,
Translate_RSQRT, Translate_POW2,
Translate_LOG2, Translate_DOT_PRODUCT_3,
Translate_DOT_PRODUCT_4, Translate_AND,
Translate_OR, Translate_XOR,
Translate_NOT, Translate_SHL,
Translate_VECTOR_SHL, Translate_SHR,
Translate_VECTOR_SHR, Translate_SHA,
Translate_VECTOR_SHA, Translate_ROTATE_LEFT,
Translate_BYTE_SWAP, Translate_CNTLZ,
Translate_INSERT, Translate_EXTRACT,
Translate_SPLAT, Translate_PERMUTE,
Translate_SWIZZLE, Translate_PACK,
Translate_UNPACK,
Translate_VECTOR_SUB, Translate_MUL,
Translate_MUL_HI, Translate_DIV,
Translate_MUL_ADD, Translate_MUL_SUB,
Translate_NEG, Translate_ABS,
Translate_SQRT, Translate_RSQRT,
Translate_POW2, Translate_LOG2,
Translate_DOT_PRODUCT_3, Translate_DOT_PRODUCT_4,
Translate_AND, Translate_OR,
Translate_XOR, Translate_NOT,
Translate_SHL, Translate_VECTOR_SHL,
Translate_SHR, Translate_VECTOR_SHR,
Translate_SHA, Translate_VECTOR_SHA,
Translate_ROTATE_LEFT, Translate_BYTE_SWAP,
Translate_CNTLZ, Translate_INSERT,
Translate_EXTRACT, Translate_SPLAT,
Translate_PERMUTE, Translate_SWIZZLE,
Translate_PACK, Translate_UNPACK,
TranslateInvalid, // Translate_COMPARE_EXCHANGE,
Translate_ATOMIC_EXCHANGE,
TranslateInvalid, // Translate_ATOMIC_ADD,

61
src/alloy/backend/x64/x64_sequences.cc
View File

@@ -2854,6 +2854,66 @@ EMITTER_OPCODE_TABLE(
SUB_V128);
// ============================================================================
// OPCODE_VECTOR_SUB
// ============================================================================
EMITTER(VECTOR_SUB, MATCH(I<OPCODE_VECTOR_SUB, V128<>, V128<>, V128<>>)) {
static void Emit(X64Emitter& e, const EmitArgType& i) {
EmitCommutativeBinaryXmmOp(e, i,
[&i](X64Emitter& e, const Xmm& dest, const Xmm& src1, const Xmm& src2) {
const TypeName part_type = static_cast<TypeName>(i.instr->flags & 0xFF);
const uint32_t arithmetic_flags = i.instr->flags >> 8;
bool is_unsigned = !!(arithmetic_flags & ARITHMETIC_UNSIGNED);
bool saturate = !!(arithmetic_flags & ARITHMETIC_SATURATE);
switch (part_type) {
case INT8_TYPE:
if (saturate) {
// TODO(benvanik): trace DID_SATURATE
if (is_unsigned) {
e.vpsubusb(dest, src1, src2);
} else {
e.vpsubsb(dest, src1, src2);
}
} else {
e.vpsubb(dest, src1, src2);
}
break;
case INT16_TYPE:
if (saturate) {
// TODO(benvanik): trace DID_SATURATE
if (is_unsigned) {
e.vpsubusw(dest, src1, src2);
} else {
e.vpsubsw(dest, src1, src2);
}
} else {
e.vpsubw(dest, src1, src2);
}
break;
case INT32_TYPE:
if (saturate) {
if (is_unsigned) {
assert_always();
} else {
assert_always();
}
} else {
e.vpsubd(dest, src1, src2);
}
break;
case FLOAT32_TYPE:
e.vsubps(dest, src1, src2);
break;
default: assert_unhandled_case(part_type); break;
}
});
}
};
EMITTER_OPCODE_TABLE(
OPCODE_VECTOR_SUB,
VECTOR_SUB);
// ============================================================================
// OPCODE_MUL
// ============================================================================
@@ -5202,6 +5262,7 @@ void RegisterSequences() {
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_ADD_CARRY);
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_VECTOR_ADD);
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_SUB);
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_VECTOR_SUB);
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_MUL);
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_MUL_HI);
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_DIV);