Screw convention; moving include files alongside source files.
They now will show up in xcode/etc.
This commit is contained in:
Ben Vanik
407
src/xenia/cpu/ppc/instr.cc
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407
src/xenia/cpu/ppc/instr.cc
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/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include <xenia/cpu/ppc/instr.h>
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#include <sstream>
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#include <xenia/cpu/ppc/instr_tables.h>
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using namespace xe::cpu::ppc;
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void InstrAccessBits::Clear() {
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spr = cr = gpr = fpr = 0;
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}
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void InstrAccessBits::Extend(InstrAccessBits& other) {
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spr |= other.spr;
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cr |= other.cr;
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gpr |= other.gpr;
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fpr |= other.fpr;
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}
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void InstrAccessBits::MarkAccess(InstrRegister& reg) {
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uint64_t bits = 0;
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if (reg.access & InstrRegister::kRead) {
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bits |= 0x1;
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}
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if (reg.access & InstrRegister::kWrite) {
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bits |= 0x2;
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}
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switch (reg.set) {
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case InstrRegister::kXER:
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spr |= bits << (2 * 0);
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break;
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case InstrRegister::kLR:
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spr |= bits << (2 * 1);
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break;
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case InstrRegister::kCTR:
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spr |= bits << (2 * 2);
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break;
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case InstrRegister::kCR:
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cr |= bits << (2 * reg.ordinal);
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break;
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case InstrRegister::kFPSCR:
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spr |= bits << (2 * 3);
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break;
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case InstrRegister::kGPR:
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gpr |= bits << (2 * reg.ordinal);
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break;
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case InstrRegister::kFPR:
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fpr |= bits << (2 * reg.ordinal);
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break;
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default:
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case InstrRegister::kVMX:
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XEASSERTALWAYS();
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break;
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}
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}
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void InstrAccessBits::Dump(std::string& out_str) {
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std::stringstream str;
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if (spr) {
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uint64_t spr_t = spr;
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if (spr_t & 0x3) {
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str << "XER [";
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str << ((spr_t & 1) ? "R" : " ");
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str << ((spr_t & 2) ? "W" : " ");
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str << "] ";
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}
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spr_t >>= 2;
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if (spr_t & 0x3) {
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str << "LR [";
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str << ((spr_t & 1) ? "R" : " ");
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str << ((spr_t & 2) ? "W" : " ");
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str << "] ";
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}
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spr_t >>= 2;
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if (spr_t & 0x3) {
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str << "CTR [";
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str << ((spr_t & 1) ? "R" : " ");
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str << ((spr_t & 2) ? "W" : " ");
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str << "] ";
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}
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spr_t >>= 2;
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if (spr_t & 0x3) {
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str << "FPCSR [";
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str << ((spr_t & 1) ? "R" : " ");
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str << ((spr_t & 2) ? "W" : " ");
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str << "] ";
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}
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spr_t >>= 2;
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}
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if (cr) {
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uint64_t cr_t = cr;
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for (size_t n = 0; n < 8; n++) {
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if (cr_t & 0x3) {
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str << "cr" << n << " [";
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str << ((cr_t & 1) ? "R" : " ");
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str << ((cr_t & 2) ? "W" : " ");
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str << "] ";
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}
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cr_t >>= 2;
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}
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}
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if (gpr) {
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uint64_t gpr_t = gpr;
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for (size_t n = 0; n < 32; n++) {
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if (gpr_t & 0x3) {
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str << "r" << n << " [";
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str << ((gpr_t & 1) ? "R" : " ");
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str << ((gpr_t & 2) ? "W" : " ");
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str << "] ";
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}
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gpr_t >>= 2;
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}
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}
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if (fpr) {
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uint64_t fpr_t = fpr;
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for (size_t n = 0; n < 32; n++) {
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if (fpr_t & 0x3) {
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str << "f" << n << " [";
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str << ((fpr_t & 1) ? "R" : " ");
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str << ((fpr_t & 2) ? "W" : " ");
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str << "] ";
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}
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fpr_t >>= 2;
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}
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}
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out_str = str.str();
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}
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void InstrDisasm::Init(std::string name, std::string info, uint32_t flags) {
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operands.clear();
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special_registers.clear();
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access_bits.Clear();
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if (flags & InstrDisasm::kOE) {
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name += "o";
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InstrRegister i = {
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InstrRegister::kXER, 0, InstrRegister::kReadWrite
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};
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special_registers.push_back(i);
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}
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if (flags & InstrDisasm::kRc) {
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name += ".";
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InstrRegister i = {
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InstrRegister::kCR, 0, InstrRegister::kWrite
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};
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special_registers.push_back(i);
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}
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if (flags & InstrDisasm::kCA) {
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InstrRegister i = {
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InstrRegister::kXER, 0, InstrRegister::kReadWrite
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};
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special_registers.push_back(i);
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}
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if (flags & InstrDisasm::kLR) {
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name += "l";
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InstrRegister i = {
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InstrRegister::kLR, 0, InstrRegister::kWrite
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};
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special_registers.push_back(i);
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}
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XEIGNORE(xestrcpya(this->name, XECOUNT(this->name), name.c_str()));
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XEIGNORE(xestrcpya(this->info, XECOUNT(this->info), info.c_str()));
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}
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void InstrDisasm::AddLR(InstrRegister::Access access) {
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InstrRegister i = {
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InstrRegister::kLR, 0, access
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};
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special_registers.push_back(i);
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}
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void InstrDisasm::AddCTR(InstrRegister::Access access) {
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InstrRegister i = {
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InstrRegister::kCTR, 0, access
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};
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special_registers.push_back(i);
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}
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void InstrDisasm::AddCR(uint32_t bf, InstrRegister::Access access) {
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InstrRegister i = {
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InstrRegister::kCR, bf, access
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};
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special_registers.push_back(i);
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}
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void InstrDisasm::AddRegOperand(
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InstrRegister::RegisterSet set, uint32_t ordinal,
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InstrRegister::Access access, std::string display) {
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InstrRegister i = {
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set, ordinal, access
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};
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InstrOperand o;
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o.type = InstrOperand::kRegister;
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o.reg = i;
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if (!display.size()) {
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std::stringstream display_out;
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switch (set) {
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case InstrRegister::kXER:
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display_out << "XER";
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break;
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case InstrRegister::kLR:
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display_out << "LR";
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break;
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case InstrRegister::kCTR:
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display_out << "CTR";
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break;
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case InstrRegister::kCR:
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display_out << "CR";
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display_out << ordinal;
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break;
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case InstrRegister::kFPSCR:
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display_out << "FPSCR";
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break;
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case InstrRegister::kGPR:
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display_out << "r";
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display_out << ordinal;
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break;
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case InstrRegister::kFPR:
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display_out << "f";
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display_out << ordinal;
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break;
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case InstrRegister::kVMX:
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display_out << "v";
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display_out << ordinal;
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break;
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}
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display = display_out.str();
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}
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XEIGNORE(xestrcpya(o.display, XECOUNT(o.display), display.c_str()));
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operands.push_back(o);
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}
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void InstrDisasm::AddSImmOperand(uint64_t value, size_t width,
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std::string display) {
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InstrOperand o;
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o.type = InstrOperand::kImmediate;
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o.imm.is_signed = true;
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o.imm.value = value;
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o.imm.width = value;
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if (display.size()) {
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XEIGNORE(xestrcpya(o.display, XECOUNT(o.display), display.c_str()));
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} else {
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const size_t max_count = XECOUNT(o.display);
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switch (width) {
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case 1:
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xesnprintfa(o.display, max_count, "%d", (int32_t)(int8_t)value);
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break;
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case 2:
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xesnprintfa(o.display, max_count, "%d", (int32_t)(int16_t)value);
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break;
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case 4:
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xesnprintfa(o.display, max_count, "%d", (int32_t)value);
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break;
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case 8:
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xesnprintfa(o.display, max_count, "%lld", (int64_t)value);
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break;
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}
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}
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operands.push_back(o);
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}
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void InstrDisasm::AddUImmOperand(uint64_t value, size_t width,
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std::string display) {
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InstrOperand o;
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o.type = InstrOperand::kImmediate;
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o.imm.is_signed = false;
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o.imm.value = value;
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o.imm.width = value;
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if (display.size()) {
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XEIGNORE(xestrcpya(o.display, XECOUNT(o.display), display.c_str()));
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} else {
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const size_t max_count = XECOUNT(o.display);
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switch (width) {
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case 1:
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xesnprintfa(o.display, max_count, "0x%.2X", (uint8_t)value);
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break;
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case 2:
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xesnprintfa(o.display, max_count, "0x%.4X", (uint16_t)value);
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break;
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case 4:
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xesnprintfa(o.display, max_count, "0x%.8X", (uint32_t)value);
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break;
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case 8:
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xesnprintfa(o.display, max_count, "0x%.16llX", value);
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break;
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}
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}
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operands.push_back(o);
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}
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int InstrDisasm::Finish() {
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for (std::vector<InstrOperand>::iterator it = operands.begin();
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it != operands.end(); ++it) {
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if (it->type == InstrOperand::kRegister) {
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access_bits.MarkAccess(it->reg);
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}
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}
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for (std::vector<InstrRegister>::iterator it = special_registers.begin();
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it != special_registers.end(); ++it) {
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access_bits.MarkAccess(*it);
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}
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return 0;
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}
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void InstrDisasm::Dump(std::string& str, size_t pad) {
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str = name;
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if (operands.size()) {
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if (pad && str.size() < pad) {
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str += std::string(pad - str.size(), ' ');
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}
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for (std::vector<InstrOperand>::iterator it = operands.begin();
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it != operands.end(); ++it) {
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str += it->display;
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if (it + 1 != operands.end()) {
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str += ", ";
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}
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}
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}
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}
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InstrType* xe::cpu::ppc::GetInstrType(uint32_t code) {
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InstrType* slot = NULL;
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switch (code >> 26) {
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case 4:
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// Opcode = 4, index = bits 5-0 (6)
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slot = &xe::cpu::ppc::tables::instr_table_4[XESELECTBITS(code, 0, 5)];
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break;
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case 19:
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// Opcode = 19, index = bits 10-1 (10)
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slot = &xe::cpu::ppc::tables::instr_table_19[XESELECTBITS(code, 1, 10)];
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break;
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case 30:
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// Opcode = 30, index = bits 4-1 (4)
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slot = &xe::cpu::ppc::tables::instr_table_30[XESELECTBITS(code, 1, 4)];
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break;
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case 31:
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// Opcode = 31, index = bits 10-1 (10)
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slot = &xe::cpu::ppc::tables::instr_table_31[XESELECTBITS(code, 1, 10)];
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break;
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case 58:
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// Opcode = 58, index = bits 1-0 (2)
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slot = &xe::cpu::ppc::tables::instr_table_58[XESELECTBITS(code, 0, 1)];
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break;
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case 59:
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// Opcode = 59, index = bits 5-1 (5)
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slot = &xe::cpu::ppc::tables::instr_table_59[XESELECTBITS(code, 1, 5)];
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break;
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case 62:
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// Opcode = 62, index = bits 1-0 (2)
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slot = &xe::cpu::ppc::tables::instr_table_62[XESELECTBITS(code, 0, 1)];
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break;
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case 63:
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// Opcode = 63, index = bits 10-1 (10)
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slot = &xe::cpu::ppc::tables::instr_table_63[XESELECTBITS(code, 1, 10)];
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break;
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default:
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slot = &xe::cpu::ppc::tables::instr_table[XESELECTBITS(code, 26, 31)];
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break;
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}
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if (!slot || !slot->opcode) {
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return NULL;
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}
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return slot;
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}
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int xe::cpu::ppc::RegisterInstrDisassemble(
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uint32_t code, InstrDisassembleFn disassemble) {
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InstrType* instr_type = GetInstrType(code);
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XEASSERTNOTNULL(instr_type);
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if (!instr_type) {
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return 1;
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}
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XEASSERTNULL(instr_type->disassemble);
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instr_type->disassemble = disassemble;
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return 0;
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}
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int xe::cpu::ppc::RegisterInstrEmit(uint32_t code, InstrEmitFn emit) {
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InstrType* instr_type = GetInstrType(code);
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XEASSERTNOTNULL(instr_type);
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if (!instr_type) {
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return 1;
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}
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XEASSERTNULL(instr_type->emit);
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instr_type->emit = emit;
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return 0;
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}
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