From 88b0aea272ac3dda9d84af3c09db36b72c65c396 Mon Sep 17 00:00:00 2001
From: "Herman S." <429230+has207@users.noreply.github.com>
Date: Wed, 15 Oct 2025 15:55:59 +0900
Subject: [PATCH] [x64] Zero extend on mov to 8bit register

---
 src/xenia/cpu/backend/x64/x64_sequences.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/xenia/cpu/backend/x64/x64_sequences.cc b/src/xenia/cpu/backend/x64/x64_sequences.cc
index c844d006c..20a7edb6d 100644
--- a/src/xenia/cpu/backend/x64/x64_sequences.cc
+++ b/src/xenia/cpu/backend/x64/x64_sequences.cc
@@ -2847,9 +2847,10 @@ struct SHL_V128 : Sequence<SHL_V128, I<OPCODE_SHL, V128Op, V128Op, I8Op>> {
     auto src1 = GetInputRegOrConstant(e, i.src1, e.xmm3);
 
     if (i.src2.is_constant) {
-      e.mov(e.GetNativeParam(1), i.src2.constant());
+      e.mov(e.GetNativeParam(0), i.src2.constant());
     } else {
-      e.mov(e.GetNativeParam(1), i.src2);
+      // Zero-extend the 8-bit register to avoid garbage in upper bits
+      e.movzx(e.GetNativeParam(0).cvt32(), i.src2);
     }
     e.lea(e.GetNativeParam(0), e.StashXmm(0, src1));
     e.CallNativeSafe(reinterpret_cast<void*>(EmulateShlV128));