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[DXBC] New tfetch: pre-swizzle signs, additive LOD + refactoring

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Triang3l
2020-06-06 19:12:34 +03:00
parent 68dd818029
commit 8a64861ec0
43 changed files with 4018 additions and 4903 deletions
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39
src/xenia/gpu/d3d12/shaders/dxbc/discrete_quad_hs.txt
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@@ -20,22 +20,23 @@
// float2 xe_point_size_min_max; // Offset: 152 Size: 8 [unused]
// float2 xe_point_screen_to_ndc; // Offset: 160 Size: 8 [unused]
// uint2 xe_sample_count_log2; // Offset: 168 Size: 8 [unused]
// uint xe_edram_resolution_square_scale;// Offset: 176 Size: 4 [unused]
// uint xe_edram_pitch_tiles; // Offset: 180 Size: 4 [unused]
// uint xe_edram_depth_base_dwords; // Offset: 184 Size: 4 [unused]
// float4 xe_color_exp_bias; // Offset: 192 Size: 16 [unused]
// uint4 xe_color_output_map; // Offset: 208 Size: 16 [unused]
// float2 xe_tessellation_factor_range;// Offset: 224 Size: 8
// float2 xe_edram_depth_range; // Offset: 232 Size: 8 [unused]
// float2 xe_edram_poly_offset_front; // Offset: 240 Size: 8 [unused]
// float2 xe_edram_poly_offset_back; // Offset: 248 Size: 8 [unused]
// uint4 xe_edram_stencil[2]; // Offset: 256 Size: 32 [unused]
// uint4 xe_edram_rt_base_dwords_scaled;// Offset: 288 Size: 16 [unused]
// uint4 xe_edram_rt_format_flags; // Offset: 304 Size: 16 [unused]
// float4 xe_edram_rt_clamp[4]; // Offset: 320 Size: 64 [unused]
// uint4 xe_edram_rt_keep_mask[2]; // Offset: 384 Size: 32 [unused]
// uint4 xe_edram_rt_blend_factors_ops;// Offset: 416 Size: 16 [unused]
// float4 xe_edram_blend_constant; // Offset: 432 Size: 16 [unused]
// uint4 xe_texture_swizzled_signs[2];// Offset: 176 Size: 32 [unused]
// uint xe_edram_resolution_square_scale;// Offset: 208 Size: 4 [unused]
// uint xe_edram_pitch_tiles; // Offset: 212 Size: 4 [unused]
// uint xe_edram_depth_base_dwords; // Offset: 216 Size: 4 [unused]
// float4 xe_color_exp_bias; // Offset: 224 Size: 16 [unused]
// uint4 xe_color_output_map; // Offset: 240 Size: 16 [unused]
// float2 xe_tessellation_factor_range;// Offset: 256 Size: 8
// float2 xe_edram_depth_range; // Offset: 264 Size: 8 [unused]
// float2 xe_edram_poly_offset_front; // Offset: 272 Size: 8 [unused]
// float2 xe_edram_poly_offset_back; // Offset: 280 Size: 8 [unused]
// uint4 xe_edram_stencil[2]; // Offset: 288 Size: 32 [unused]
// uint4 xe_edram_rt_base_dwords_scaled;// Offset: 320 Size: 16 [unused]
// uint4 xe_edram_rt_format_flags; // Offset: 336 Size: 16 [unused]
// float4 xe_edram_rt_clamp[4]; // Offset: 352 Size: 64 [unused]
// uint4 xe_edram_rt_keep_mask[2]; // Offset: 416 Size: 32 [unused]
// uint4 xe_edram_rt_blend_factors_ops;// Offset: 448 Size: 16 [unused]
// float4 xe_edram_blend_constant; // Offset: 464 Size: 16 [unused]
//
// }
//
@@ -89,7 +90,7 @@ dcl_tessellator_domain domain_quad
dcl_tessellator_partitioning partitioning_integer
dcl_tessellator_output_primitive output_triangle_cw
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][15], immediateIndexed, space=0
dcl_constantbuffer CB0[0:0][17], immediateIndexed, space=0
hs_control_point_phase
dcl_input vOutputControlPointID
dcl_input v[4][0].x
@@ -108,7 +109,7 @@ dcl_output_siv o3.x, finalQuadVeq1EdgeTessFactor
dcl_temps 1
dcl_indexrange o0.x 4
mov r0.x, vForkInstanceID.x
mov o[r0.x + 0].x, CB0[0][14].y
mov o[r0.x + 0].x, CB0[0][16].y
ret
hs_fork_phase
dcl_hs_fork_phase_instance_count 2
@@ -118,6 +119,6 @@ dcl_output_siv o5.x, finalQuadVInsideTessFactor
dcl_temps 1
dcl_indexrange o4.x 2
mov r0.x, vForkInstanceID.x
mov o[r0.x + 4].x, CB0[0][14].y
mov o[r0.x + 4].x, CB0[0][16].y
ret
// Approximately 9 instruction slots used