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Interrupts fire on the right 'thread', ringbuffer work,

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Ben Vanik
2013-10-19 11:50:01 -07:00
parent 6db8c6c961
commit 90bc6ad1a8
10 changed files with 145 additions and 48 deletions
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9
src/xenia/gpu/xenos/packets.h
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@@ -67,9 +67,16 @@ enum Type3Opcode {
PM4_SET_BIN_SELECT = 0x51, // sets the 64-bit BIN_SELECT register in the PFP
PM4_CONTEXT_UPDATE = 0x5e, // updates the current context, if needed
PM4_INTERRUPT = 0x40, // generate interrupt from the command stream
PM4_INTERRUPT = 0x54, // generate interrupt from the command stream
PM4_IM_STORE = 0x2c, // copy sequencer instruction memory to system memory
// Tiled rendering:
// https://www.google.com/patents/US20060055701
PM4_SET_BIN_MASK_LO = 0x60,
PM4_SET_BIN_MASK_HI = 0x61,
PM4_SET_BIN_SELECT_LO = 0x62,
PM4_SET_BIN_SELECT_HI = 0x63,
};

2
src/xenia/gpu/xenos/register_table.inc
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@@ -98,6 +98,8 @@ XE_GPU_REGISTER(0x2182, dword, SQ_INTERPOLATOR_CNTL)
XE_GPU_REGISTER(0x2183, dword, SQ_WRAPPING_0)
XE_GPU_REGISTER(0x2184, dword, SQ_WRAPPING_1)
XE_GPU_REGISTER(0x21F9, dword, VGT_EVENT_INITIATOR)
XE_GPU_REGISTER(0x2200, dword, RB_DEPTHCONTROL)
XE_GPU_REGISTER(0x2201, dword, RB_BLENDCONTROL_0)
XE_GPU_REGISTER(0x2202, dword, RB_COLORCONTROL)