[GPU] Ownership-transfer-based RT cache, 3x3 resolution scaling

The ROV path is also disabled by default because of lower performance

src/xenia/gpu/d3d12/shaders/dxbc/clear_uint2_ps.txt

@@ -0,0 +1,41 @@
+//
+// Generated by Microsoft (R) HLSL Shader Compiler 10.1
+//
+//
+// Buffer Definitions: 
+//
+// cbuffer XeClearConstants
+// {
+//
+//   uint2 xe_clear_value;              // Offset:    0 Size:     8
+//
+// }
+//
+//
+// Resource Bindings:
+//
+// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
+// ------------------------------ ---------- ------- ----------- ------- -------------- ------
+// XeClearConstants                  cbuffer      NA          NA     CB0            cb0      1 
+//
+//
+//
+// Input signature:
+//
+// Name                 Index   Mask Register SysValue  Format   Used
+// -------------------- ----- ------ -------- -------- ------- ------
+// no Input
+//
+// Output signature:
+//
+// Name                 Index   Mask Register SysValue  Format   Used
+// -------------------- ----- ------ -------- -------- ------- ------
+// SV_Target                0   xy          0   TARGET    uint   xy  
+//
+ps_5_1
+dcl_globalFlags refactoringAllowed
+dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0
+dcl_output o0.xy
+mov o0.xy, CB0[0][0].xyxx
+ret 
+// Approximately 2 instruction slots used