[D3D12] Adaptive tessellation of triangle patches
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Triang3l
160
src/xenia/gpu/d3d12/shaders/dxbc/adaptive_triangle_hs.txt
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160
src/xenia/gpu/d3d12/shaders/dxbc/adaptive_triangle_hs.txt
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//
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// Generated by Microsoft (R) HLSL Shader Compiler 10.1
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//
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//
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// Note: shader requires additional functionality:
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// UAVs at every shader stage
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//
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//
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// Buffer Definitions:
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//
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// cbuffer xe_system_cbuffer
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// {
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//
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// uint xe_flags; // Offset: 0 Size: 4
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// uint xe_vertex_index_endian_and_edge_factors;// Offset: 4 Size: 4
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// int xe_vertex_base_index; // Offset: 8 Size: 4
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// uint xe_pixel_pos_reg; // Offset: 12 Size: 4 [unused]
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// float3 xe_ndc_scale; // Offset: 16 Size: 12 [unused]
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// float xe_pixel_half_pixel_offset; // Offset: 28 Size: 4 [unused]
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// float3 xe_ndc_offset; // Offset: 32 Size: 12 [unused]
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// int xe_alpha_test; // Offset: 44 Size: 4 [unused]
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// float2 xe_point_size; // Offset: 48 Size: 8 [unused]
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// float2 xe_point_size_min_max; // Offset: 56 Size: 8 [unused]
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// float2 xe_point_screen_to_ndc; // Offset: 64 Size: 8 [unused]
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// uint2 xe_sample_count_log2; // Offset: 72 Size: 8 [unused]
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// float2 xe_alpha_test_range; // Offset: 80 Size: 8 [unused]
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// uint xe_edram_pitch_tiles; // Offset: 88 Size: 4 [unused]
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// uint xe_edram_depth_base_dwords; // Offset: 92 Size: 4 [unused]
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// float4 xe_color_exp_bias; // Offset: 96 Size: 16 [unused]
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// uint4 xe_color_output_map; // Offset: 112 Size: 16 [unused]
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// float2 xe_tessellation_factor_range;// Offset: 128 Size: 8
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// float2 xe_edram_depth_range; // Offset: 136 Size: 8 [unused]
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// float2 xe_edram_poly_offset_front; // Offset: 144 Size: 8 [unused]
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// float2 xe_edram_poly_offset_back; // Offset: 152 Size: 8 [unused]
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// uint xe_edram_resolution_scale_log2;// Offset: 160 Size: 4 [unused]
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// uint xe_edram_stencil_reference; // Offset: 164 Size: 4 [unused]
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// uint xe_edram_stencil_read_mask; // Offset: 168 Size: 4 [unused]
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// uint xe_edram_stencil_write_mask; // Offset: 172 Size: 4 [unused]
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// uint4 xe_edram_stencil_front; // Offset: 176 Size: 16 [unused]
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// uint4 xe_edram_stencil_back; // Offset: 192 Size: 16 [unused]
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// uint4 xe_edram_base_dwords; // Offset: 208 Size: 16 [unused]
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// uint4 xe_edram_rt_flags; // Offset: 224 Size: 16 [unused]
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// uint4 xe_edram_rt_pack_width_low; // Offset: 240 Size: 16 [unused]
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// uint4 xe_edram_rt_pack_offset_low; // Offset: 256 Size: 16 [unused]
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// uint4 xe_edram_rt_pack_width_high; // Offset: 272 Size: 16 [unused]
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// uint4 xe_edram_rt_pack_offset_high;// Offset: 288 Size: 16 [unused]
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// uint4 xe_edram_load_mask_rt01; // Offset: 304 Size: 16 [unused]
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// uint4 xe_edram_load_mask_rt23; // Offset: 320 Size: 16 [unused]
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// float4 xe_edram_load_scale_rt01; // Offset: 336 Size: 16 [unused]
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// float4 xe_edram_load_scale_rt23; // Offset: 352 Size: 16 [unused]
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// uint4 xe_edram_blend_rt01; // Offset: 368 Size: 16 [unused]
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// uint4 xe_edram_blend_rt23; // Offset: 384 Size: 16 [unused]
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// float4 xe_edram_blend_constant; // Offset: 400 Size: 16 [unused]
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// float4 xe_edram_store_min_rt01; // Offset: 416 Size: 16 [unused]
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// float4 xe_edram_store_min_rt23; // Offset: 432 Size: 16 [unused]
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// float4 xe_edram_store_max_rt01; // Offset: 448 Size: 16 [unused]
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// float4 xe_edram_store_max_rt23; // Offset: 464 Size: 16 [unused]
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// float4 xe_edram_store_scale_rt01; // Offset: 480 Size: 16 [unused]
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// float4 xe_edram_store_scale_rt23; // Offset: 496 Size: 16 [unused]
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//
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// }
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//
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//
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// Resource Bindings:
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//
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// Name Type Format Dim ID HLSL Bind Count
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// ------------------------------ ---------- ------- ----------- ------- -------------- ------
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// xe_shared_memory_srv texture byte r/o T0 t0 1
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// xe_shared_memory_uav UAV byte r/w U0 u0 1
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// xe_system_cbuffer cbuffer NA NA CB0 cb0 1
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//
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//
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//
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// Patch Constant signature:
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//
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// Name Index Mask Register SysValue Format Used
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// -------------------- ----- ------ -------- -------- ------- ------
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// SV_TessFactor 0 x 0 TRIEDGE float x
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// SV_TessFactor 1 x 1 TRIEDGE float x
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// SV_TessFactor 2 x 2 TRIEDGE float x
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// SV_InsideTessFactor 0 x 3 TRIINT float x
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//
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//
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// Input signature:
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//
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// Name Index Mask Register SysValue Format Used
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// -------------------- ----- ------ -------- -------- ------- ------
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// no Input
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//
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// Output signature:
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//
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// Name Index Mask Register SysValue Format Used
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// -------------------- ----- ------ -------- -------- ------- ------
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// no Output
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// Tessellation Domain # of control points
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// -------------------- --------------------
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// Triangle 3
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//
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// Tessellation Output Primitive Partitioning Type
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// ------------------------------ ------------------
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// Clockwise Triangles Even Fractional
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//
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hs_5_1
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hs_decls
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dcl_input_control_point_count 3
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dcl_output_control_point_count 3
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dcl_tessellator_domain domain_tri
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dcl_tessellator_partitioning partitioning_fractional_even
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dcl_tessellator_output_primitive output_triangle_cw
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dcl_globalFlags refactoringAllowed
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dcl_constantbuffer CB0[0:0][9], immediateIndexed, space=0
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dcl_resource_raw T0[0:0], space=0
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dcl_uav_raw U0[0:0], space=0
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hs_fork_phase
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dcl_input vPrim
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dcl_output_siv o0.x, finalTriUeq0EdgeTessFactor
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dcl_output_siv o1.x, finalTriVeq0EdgeTessFactor
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dcl_output_siv o2.x, finalTriWeq0EdgeTessFactor
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dcl_temps 3
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imul null, r0.x, CB0[0][0].z, l(3)
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imad r0.x, vPrim, l(3), r0.x
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and r0.yzw, CB0[0][0].yyxy, l(0, 0x1ffffffc, 1, 2)
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ishl r0.x, r0.x, l(2)
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iadd r0.x, r0.x, r0.y
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if_nz r0.z
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ld_raw r1.xyz, r0.x, U0[0].xyzx
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else
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ld_raw r1.xyz, r0.x, T0[0].xyzx
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endif
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ushr r0.x, CB0[0][0].y, l(1)
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xor r0.x, r0.x, CB0[0][0].y
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and r0.x, r0.x, l(1)
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if_nz r0.x
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ishl r0.xyz, r1.xyzx, l(8, 8, 8, 0)
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and r0.xyz, r0.xyzx, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0)
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ushr r2.xyz, r1.xyzx, l(8, 8, 8, 0)
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and r2.xyz, r2.xyzx, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0)
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iadd r1.xyz, r0.xyzx, r2.xyzx
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endif
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if_nz r0.w
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ushr r0.xyz, r1.xyzx, l(16, 16, 16, 0)
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bfi r1.xyz, l(16, 16, 16, 0), l(16, 16, 16, 0), r1.xyzx, r0.xyzx
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endif
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add r0.xyz, r1.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
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max r0.xyz, r0.xyzx, CB0[0][8].xxxx
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min r0.xyz, r0.xyzx, CB0[0][8].yyyy
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mov o0.x, r0.z
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mov o1.x, r0.y
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mov o2.x, r0.x
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ret
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hs_join_phase
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dcl_input vpc0.x
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dcl_input vpc1.x
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dcl_input vpc2.x
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dcl_output_siv o3.x, finalTriInsideTessFactor
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dcl_temps 1
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min r0.x, vpc0.x, vpc1.x
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min o3.x, r0.x, vpc2.x
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ret
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// Approximately 34 instruction slots used
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