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Moving LoadAcquire/StoreRelease behavior up into HIR.

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This commit is contained in:
Ben Vanik
2014-01-04 00:50:48 -08:00
parent 88b631b160
commit 93ea56179a
11 changed files with 97 additions and 197 deletions
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2
src/xenia/atomic.h
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@@ -53,6 +53,8 @@ typedef OSQueueHead xe_atomic_stack_t;
((void)InterlockedExchangeSubtract((volatile unsigned*)value, amount))
#define xe_atomic_exchange_32(newValue, value) \
InterlockedExchange((volatile LONG*)value, newValue)
#define xe_atomic_exchange_64(newValue, value) \
InterlockedExchange64((volatile LONGLONG*)value, newValue)
#define xe_atomic_cas_32(oldValue, newValue, value) \
(InterlockedCompareExchange((volatile LONG*)value, newValue, oldValue) == oldValue)

11
src/xenia/cpu/xenon_thread_state.cc
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@@ -36,13 +36,14 @@ XenonThreadState::XenonThreadState(
xe_zero_struct(context_, sizeof(PPCContext));
// Stash pointers to common structures that callbacks may need.
context_->membase = memory_->membase();
context_->runtime = runtime;
context_->thread_state = this;
context_->reserve_address = memory_->reserve_address();
context_->membase = memory_->membase();
context_->runtime = runtime;
context_->thread_state = this;
// Set initial registers.
context_->r[1] = stack_address_ + stack_size;
context_->r[13] = thread_state_address_;
context_->r[1] = stack_address_ + stack_size;
context_->r[13] = thread_state_address_;
raw_context_ = context_;